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參數(shù)資料
| 型號： | M80C86 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS 16-Bit Microcontroller(16位CHMOS 微處理器) |
| 中文描述： | CHMOS 16位微控制器（16位CHMOS微處理器） |
| 文件頁數(shù)： | 3/19頁 |
| 文件大?。?/td> | 277K |
| 代理商： | M80C86 |
M80C86/M80C86-2
Table 1. Pin Description
(Continued)
Symbol
Pin No.
Type
Name and Function
RD
32
O
READ:
Read strobe indicates that the processor is performing a
memory of I/O read cycle, depending on the state of the S
2
pin.
This signal is used to read devices which reside on the M80C86
local bus. RD is active LOW during T
2
, T
3
and T
W
of any read cycle,
and is guaranteed to remain HIGH in T
2
until the M80C86 local bus
has floated.
This floats to 3-state OFF in ‘‘hold acknowledge.’’
READY
22
I
READY:
is the acknowledgement from the addressed memory or
I/O device that it will complete the data transfer. The READY signal
from memory/IO is synchronized by the M82C84A Clock Generator
to form READY. This signal is active HIGH. The M80C86 READY
input is not synchronized. Correct operation is not guaranteed if the
setup and hold times are not met.
INTR
18
I
INTERRUPT REQUEST:
is a level triggered input which is sampled
during the last clock cycle of each instruction to determine if the
processor should enter into an interrupt acknowledge operation. A
subroutine is vectored to via an interrupt vector lookup table
located in system memory. It can be internally masked by software
resetting the interrupt enable bit. INTR is internally synchronized.
This signal is active HIGH.
TEST
23
I
TEST:
input is examined by the ‘‘Wait’’ instruction. If the TEST input
is LOW execution continues, otherwise the processor waits in an
‘‘Idle’’ state. This input is synchronized internally during each clock
cycle on the leading edge of CLK.
NMI
17
I
NON-MASKABLE INTERRUPT:
an edge triggered input which
causes a type 2 interrupt. A subroutine is vectored to via an
interrupt vector lookup table located in system memory. NMI is not
maskable internally by software. A transition from a LOW to HIGH
initiates the interrupt at the end of the current instruction. This input
is internally synchronized.
RESET
21
I
RESET:
causes the processor to immediately terminate its present
activity. The signal must be active HIGH for at least four clock
cycles. It restarts execution, as described in the Instruction Set
description, when RESET returns LOW. RESET is internally
synchronized.
CLK
19
I
CLOCK:
provides the basic timing for the processor and bus
controller. It is asymmetric with a 33% duty cycle to provide
optimized internal timing.
V
CC
40
V
CC
:
a
5V power supply pin.
GND
1, 20
GROUND:
Both must be connected.
MN/MX
33
I
MINIMUM/MAXIMUM:
indicates what mode the processor is to
operate in. The two modes are discussed in the following sections.
3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M80C86-20 | CHMOS 16-Bit Microcontroller(16位CHMOS 微處理器) |
| M80C86-2 | 16-BIT CHMOS MICROPROCESSOR |
| M8216 | 4-BIT PARALLEL BIDIRECTIONAL BUS DRIVER |
| M8226 | 4-BIT PARALLEL BIDIRECTIONAL BUS DRIVER |
| M8284A | CLOCK GENERATOR AND DRIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M80C86-2 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:16-BIT CHMOS MICROPROCESSOR |
| M80C86A-2 | 制造商:OK International 功能描述:Microprocessor, 16 Bit, 56 Pin, Plastic, QFP |
| M80C88 | 制造商:OK International 功能描述:Microprocessor, 16 Bit, 40 Pin, Plastic, DIP |
| M80C88A | 制造商:OK International 功能描述:Microprocessor, 16 Bit, 56 Pin, Plastic, QFP |
| M80C88A-2 | 制造商:INTOKI 功能描述: |
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