參數(shù)資料
型號(hào)： M80C86-2
廠商： Intel Corp.
英文描述： 16-BIT CHMOS MICROPROCESSOR
中文描述： 16位微處理器CHMOS
文件頁(yè)數(shù)： 6/19頁(yè)
文件大?。?/td> 277K
代理商： M80C86-2
M80C86/M80C86-2
Table 1. Pin Description
(Continued)
Symbol
Pin No.
Type
Name and Function
DEN
26
O
DATA ENABLE:
provided as an output enable for the transceiver in
a minimum system which uses the transceiver. DEN is active LOW
during each memory and I/O access and for INTA cycles. For a
read or INTA cycle it is active from the middle of T
2
until the middle
of T
4
, while for a write cycle it is active from the beginning of T
2
until the middle of T
4
. DEN floats to 3-state OFF
(1)
in local bus
‘‘hold acknowledge.’’
HOLD,
HLDA
31, 30
I/O
HOLD:
indicates that another master is requesting a local bus
‘‘hold.’’ To be acknowledged, HOLD must be active HIGH. The
processor receiving the ‘‘hold’’ request will issue HLDA (HIGH) as
an acknowledgement in the middle of a T
1
clock cycle.
Simultaneous with the issuance of HLDA the processor will float the
local bus and control lines. After HOLD is detected as being LOW,
the processor will LOWer the HLDA, and when the processor
needs to run another cycle, it will again drive the local bus and
control lines.
The same rules as for RQ/GT apply regarding when the local bus
will be released.
HOLD is not an asynchronous input. External synchronization
should be provided if the system cannot otherwise guarantee the
setup time.
NOTE:
1. See the section on Bus Hold Circuitry.
FUNCTIONAL DESCRIPTION
STATIC OPERATION
All M80C86 circuitry is of static design. Internal reg-
isters, counters and latches are static and require no
refresh as with dynamic circuit design. This elimi-
nates the minimum operating frequency restriction
placed on other microprocessors. The CMOS
M80C86 can operate from DC to the appropriate up-
per frequency limit. The processor clock may be
stopped in either state (high/low) and held there in-
definitely. This type of operation is especially useful
for system debug or power critical applications.
The M80C86 can be single stepped using only the
CPU clock. This state can be maintained as long as
is necessary. Single step clock operation allows sim-
ple interface circuitry to provide critical information
for bringing up your system.
Static design also allows very low frequency opera-
tion. In a power critical situation, this can provide
extremely low power operation since M80C86 power
dissipation is directly related to operating frequency.
As the system frequency is reduced, so is the oper-
ating power until, ultimately, at a DC input frequency,
the M80C86 power requirement is the standby cur-
rent.
6
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