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參數(shù)資料
| 型號(hào)： | M80C86-2 |
| 廠商： | Intel Corp. |
| 英文描述： | 16-BIT CHMOS MICROPROCESSOR |
| 中文描述： | 16位微處理器CHMOS |
| 文件頁(yè)數(shù)： | 2/19頁(yè) |
| 文件大?。?/td> | 277K |
| 代理商： | M80C86-2 |
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M80C86/M80C86-2
Table 1. Pin Description
The following pin function descriptions are for M80C86 systems in either minimum or maximum mode. The
‘‘Local Bus’’ in these descriptions is the direct multiplexed bus interface connection to the M80C86 (without
regard to additional bus buffers).
Symbol
Pin No.
Type
Name and Function
AD
15
–AD
0
2–16, 39
I/O
ADDRESS DATA BUS:
These lines constitute the time multiplexed
memory/IO address (T
1
) and data (T
2
, T
3
, T
W
, T
4
) bus. A
0
is
analogous to BHE for the lower byte of the data bus, pins D
7
–D
0
. It
is LOW during T
1
when a byte is to be transferred on the lower
portion of the bus in memory or I/O operations. Eight-bit oriented
devices tied to the lower half would normally use A
0
to condition
chip select functions. (See BHE.) These lines are active HIGH and
float to 3-state OFF
(1)
during interrupt acknowledge and local bus
‘‘hold acknowledge.’’
A
19
/S
6
,
A
18
/S
5
,
A
17
/S
4
,
A
16
/S
3
35–38
O
ADDRESS/STATUS:
During T
1
these are the four most significant
address lines for memory operations. During I/O operations
these lines are LOW. During memory and I/O operations,
status information is available on these lines during T
2
, T
3
, T
W
,
and T
4
. The status of the interrupt enable FLAG bit (S
5
) is updated
at the beginning of each CLK cycle. A
17
/S
4
and A
16
/S
3
are
encoded as shown.
This information indicates which relocation register is presently
being used for data accessing.
These lines float to 3-state OFF
(1)
during local bus ‘‘hold
acknowledge.’’
A
17
/S
4
A
16
/S
3
Characteristics
0 (LOW)
0
1 (HIGH)
1
S
6
is 0
(LOW)
0
1
0
1
Alternate Data
Stack
Code or None
Data
BHE/S
7
34
O
BUS HIGH ENABLE/STATUS:
During T
1
the bus high enable signal
(BHE) should be used to enable data onto the most significant half
of the data bus, pins D
15
–D
8
. Eight-bit oriented devices tied to the
upper half of the bus would normally use BHE to condition chip
select functions. BHE is LOW during T
1
for read, write, and interrupt
acknowledge cycles when a byte is to be transferred on the high
portion of the bus. The S
7
status information is available during T
2
,
T
3
, and T
4
. The signal is active LOW, and floats to 3-state OFF
(1)
in
‘‘hold.’’ It is LOW during T
1
for the first interrupt acknowledge cycle.
BHE
A
0
Characteristics
0
0
0
1
Whole word
Upper byte from/
to odd address
Lower byte from/
to even address
None
1
0
1
1
2
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