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參數(shù)資料
| 型號： | M80C86-20 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS 16-Bit Microcontroller(16位CHMOS 微處理器) |
| 中文描述： | CHMOS 16位微控制器（16位CHMOS微處理器） |
| 文件頁數(shù)： | 5/19頁 |
| 文件大?。?/td> | 277K |
| 代理商： | M80C86-20 |
M80C86/M80C86-2
Table 1. Pin Description
(Continued)
Symbol
Pin No.
Type
Name and Function
If the local bus is idle when the request is made the two possible
events will follow:
1. Local bus will be released during the next clock.
2. A memory cycle will start within 3 clocks. Now the four rules for a
currently active memory cycle apply with condition number 1 already
satisfied.
LOCK
29
O
LOCK:
output indicates that other system bus masters are not to gain
control of the system bus while LOCK is active LOW. The LOCK
signal is activated by the ‘‘LOCK’’ prefix instruction and remains
active until the completion of the next instruction. This signal is active
LOW, and floats to 3-state OFF
(1)
in ‘‘hold acknowledge.’’
QS
1
, QS
0
24, 25
O
QUEUE STATUS:
The queue status is valid during the CLK cycle
after which the queue operation is performed.
QS
1
and QS
0
provide status to allow external tracking of the internal
M80C86 instruction queue.
QS
1
QS
0
Characteristics
0 (LOW)
0
1 (HIGH)
1
0
1
0
1
No Operation
First Byte of Op Code from Queue
Empty the Queue
Subsequent Byte from Queue
The following pin function descriptions are for the M80C86 in minimum mode (i.e., MN/MX
e
V
CC
). Only the
pin functions which are unique to minimum mode are described; all other pin functions are described above.
M/IO
28
O
STATUS LINE:
logically equivalent to S
2
in the maximum mode. It
is used to distinguish a memory access from an I/O access. M/IO
becomes valid in the T
4
preceding a bus cycle and remains valid
until the final T
4
of the cycle (M
e
HIGH, IO
e
LOW). M/IO floats to
3-state OFF
(1)
in local bus ‘‘hold acknowledge.’’
WR
29
O
WRITE:
indicates that the processor is performing a write memory
or write I/O cycle, depending on the state of the M/IO signal. WR is
active for T
2
, T
3
and T
W
of any write cycle. It is active LOW, and
floats to 3-state OFF
(1)
in local bus ‘‘hold acknowledge.’’
INTA
24
O
INTA is used as a read strobe for interrupt acknowledge cycles. It is
active LOW during T
2
, T
3
and T
W
of each interrupt acknowledge
cycle.
ALE
25
O
ADDRESS LATCH ENABLE:
provided by the processor to latch
the address into an address latch. It is a HIGH pulse active during
T
1
of any bus cycle. Note that ALE is never floated.
DT/R
27
O
DATA TRANSMIT/RECEIVE:
needed in minimum system that
desires to use a data bus transceiver. It is used to control the
direction of data flow through the transceiver. Logically DT/R is
equivalent to S
1
in the maximum mode, and its timing is the same
as for M/IO. (T
e
HIGH, R
e
LOW.) This signal floats to 3-state
OFF
(1)
in local bus ‘‘hold acknowledge.’’
5
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