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參數(shù)資料
| 型號： | M80C86-20 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS 16-Bit Microcontroller(16位CHMOS 微處理器) |
| 中文描述： | CHMOS 16位微控制器（16位CHMOS微處理器） |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 277K |
| 代理商： | M80C86-20 |
M80C86/M80C86-2
Table 1. Pin Description
(Continued)
The following pin function descriptions are for the M80C86/M82C88 system in maximum mode (i.e.,
MN/MX
e
V
SS
). Only the pin functions which are unique to maximum mode are described; all other pin func-
tions are as described above.
Symbol
Pin No.
Type
Name and Function
S
2
, S
1
, S
0
26–28
O
STATUS:
active during T
4
, T
1
, and T
2
and is returned to the passive
state (1,1,1) during T
3
or during T
W
when READY is HIGH. This
status is used by the M82C88 Bus Controller to generate all memory
and I/O access control signals. Any change by S
2
, S
1
, S
0
during T
4
is used to indicate the beginning of a bus cycle, and the return to the
passive state in T
3
or T
W
is used to indicate the end of a bus cycle.
These signals float to 3-state OFF
(1)
in ‘‘hold acknowledge.’’ These
status lines are encoded as shown.
S
2
S
1
S
0
Characteristics
0 (LOW)
0
0
Interrupt
Acknowledge
Read I/O Port
Write I/O Port
Halt
Code Access
Read Memory
Write Memory
Passive
0
0
0
1 (HIGH)
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
RQ/GT
0,
RQ/GT
1
30, 31
I/O
REQUEST/GRANT:
pins are used by other local bus masters to
force the processor to release the local bus at the end of the
processor’s current bus cycle. Each pin is bidirectional with RQ/GT
0
having higher priority than RQ/GT
1
. RQ/GT has an internal pull-up
resistor so may be left unconnected. The request/grant sequence is
as follows (see timing diagram):
1. A pulse of 1 CLK wide from another local bus master indicates a
local bus request (‘‘hold’’) to the M80C86 (pulse 1).
2. During a T
4
or T
1
clock cycle, a pulse 1 CLK wide from the
M80C86 to the requesting master (pulse 2), indicates that the
M80C86 has allowed the local bus to float and that it will enter the
‘‘hold acknowledge’’ state at the next CLK. The CPU’s bus interface
unit is disconnected logically from the local bus during ‘‘hold
acknowledge.’’
3. A pulse 1 CLK wide from the requesting master indicates to the
M80C86 (pulse 3) that the ‘‘hold’’ request is about to end and that
M80C86 can reclaim the local bus at the next CLK.
Each master-master exchange of the local bus is a sequence of 3
pulses. There must be one dead CLK cycle after each bus exchange.
Pulses are active LOW.
If the request is made while the CPU is performing a memory cycle, it
will release the local bus during T
4
of the cycle when all the following
conditions are met:
1. Request occurs on or before T
2
.
2. Current cycle is not the low byte of a word (on an odd address).
3. Current cycle is not the first acknowledge of an interrupt
acknowledge sequence.
4. A locked instruction is not currently executing.
4
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