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參數(shù)資料
| 型號(hào)： | M80C51FB |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS Single-Chip 8-Bit Microcontroller(CHMOS單芯片8位微控制器) |
| 中文描述： | CHMOS單片8位微控制器（CHMOS單芯片8位微控制器） |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 184K |
| 代理商： | M80C51FB |
M80C51FB
D.C. CHARACTERISTICS:
(Over Specified Operating Conditions) (Continued)
Symbol
Parameter
Min
Max
Unit
Test Conditions
V
OH1
Output High Voltage
(Port 0 in External Bus Mode,
ALE, PSEN)
V
CC
b
0.3
V
CC
b
0.7
V
CC
b
1.5
V
I
OH
e b
200
m
A (Note 2)
I
OH
e b
3.2 mA
I
OH
e b
7.0 mA (Note 4)
V
IN
e
0.45V
V
V
I
IL
Logical 0 Input Current
(Ports 1, 2, and 3)
b
75
m
A
I
LI
Input leakage Current (Port 0)
g
10
m
A
0.45V
k
V
IN
k
V
CC
V
IN
e
2V
I
TL
Logical 1 to 0 Transition Current
(Ports 1, 2, and 3)
b
750
m
A
RRST
RST Pulldown Resistor
40
225
K
X
CIO
Pin Capacitance
10
pF
@
1 MHz, 25
§
C
I
CC
Power Supply Current:
Active Mode
@
16 MHz
Idle Mode
@
16 MHz
Power Down Mode
@
16 MHz
(Note 3)
45
15
130
mA
mA
m
A
NOTES:
1. Capacitive loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V
OL
s of ALE and Ports
1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to
0 transitions during bus operations. In applications where capacitance loading exceeds 100 pFs, the noise pulse on the ALE
signal may exceed 0.8V. In these cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an Address Latch
with a Schmitt Trigger Strobe input.
2. Capacitive loading on Ports 0 and 2 cause the V
OH
on ALE and PSEN to drop below the V
CC
b
0.3 specification when
the address lines are stabilizing.
3. See Figures 5–8 for load circuits. Minimum V
CC
for Power Down is 2V.
4. Care must be taken not to exceed the maximum allowable power dissipation.
5. Under steady state (non-transient) conditions, I
must be externally limited as follows:
Maximum I
OL
per port pin:
10mA
Maximum I
OL
per 8-bit portD
Port 0:
26 mA
Ports 1, 2 and 3:
15 mA
Maximum total I
OL
for all output pins:
71 mA
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test conditions.
271172–6
All other pins disconnected
TCLCH
e
TCHCL
e
5 ns
Figure 5. I
CC
Load Circuit Active Mode
271172–7
All other pins disconnected
TCLCH
e
TCHCL
e
5 ns
Figure 6. I
CC
Load Circuit Idle Mode
7
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