參數(shù)資料
型號(hào): M74HC191C1R
廠商: 意法半導(dǎo)體
元件分類: TVS-瞬態(tài)抑制二極管
英文描述: 16-Bit Transparent D-Type Latches With 3-State Outputs 48-SSOP -40 to 85
中文描述: 4上/下計(jì)數(shù)器位同步
文件頁(yè)數(shù): 8/14頁(yè)
文件大?。?/td> 299K
代理商: M74HC191C1R
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Symbol
Parameter
Test Conditions
Value
-40 to 85
o
C
74HC
Min.
Unit
V
CC
(V)
T
A
= 25
o
C
54HC and 74HC
Min.
Typ.
84
21
18
39
13
11
63
21
18
64
18
15
5
25
37
30
44
40
10
-55 to 125
o
C
54HC
Min.
Max.
175
35
30
105
21
18
180
36
31
160
32
27
Max.
220
44
37
130
26
22
225
45
38
200
40
34
Max.
265
53
45
160
32
27
270
54
46
240
48
41
t
PLH
t
PHL
Propagation
Delay Time
(DATA - Q)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
ns
t
PLH
t
PHL
Propagation
Delay Time
(ENABLE - RCO)
ns
t
PLH
t
PHL
Propagation
Delay Time
(D/U - RCO)
ns
t
PLH
t
PHL
Propagation
Delay Time
(D/U - MAX/MIN)
ns
f
MAX
Maximum Clock
Frequency
9
4
3.4
17
20
MHz
20
24
t
W(H)
t
W(L)
Minimum Pulse
Width
(CLOCK)
100
20
17
75
15
13
175
35
30
50
10
9
0
0
0
50
10
9
10
125
25
21
95
19
16
220
44
37
60
12
11
0
0
0
60
12
11
10
150
30
26
110
22
19
265
53
45
75
15
13
0
0
0
5
15
13
10
ns
9
t
W(L)
Minimum Pulse
Width
(LOAD)
36
9
8
80
20
17
16
4
3
ns
t
s
Minimum Set-up
Time
(SI, PI - CK)
ns
t
s
Minimum Set-up
Time
(S0, S1 - CK)
ns
t
h
Minimum Hold
Time
ns
t
REM
Minimum
Removal Time
12
3
3
5
111
112
ns
C
IN
Input Capacitance
Power Dissipation
Capacitance
pF
C
PD
(*)
for HC190
for HC191
pF
(*) C
PD
isdefined asthe value ofthe IC’sinternal equivalent capactance which is calculated from the operating current consumption without load.
(Refer to Test Circuit).Average operting current can be obtained by thefollowingequation. I
CC
(opr) = C
PD
V
CC
f
IN
+ I
CC
M54/M74HC190/191
8/14
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