參數(shù)資料
型號(hào): M74HC191B1R
廠商: 意法半導(dǎo)體
英文描述: 10-Bit, 3 us Quad DAC, Serial Input, Simultaneous Update, Programmable Settling Time, PowerDown 16-SOIC -40 to 85
中文描述: 4上/下計(jì)數(shù)器位同步
文件頁數(shù): 1/14頁
文件大?。?/td> 299K
代理商: M74HC191B1R
M54/M74HC190
M54/M74HC191
October 1992
4 BIT SYNCHRONOUS UP/DOWN COUNTERS
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
I
OH
= I
OL
= 4 mA(MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN ANDFUNCTION COMPATIBLE
WITH 54/74LS190/191
B1R
(Plastic Package)
ORDER CODES :
M54HCXXXF1R
M74HCXXXB1R
M74HCXXXM1R
M74HCXXXC1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
DESCRIPTION
.
HIGH SPEED
f
MAX
= 48 MHz (TYP.) AT V
CC
= 5 V
The M54/74HC190/191 are high speedCMOS4-BIT
SYNCHRONOUS UP/DOWN COUNTERS fabri-
catedinsilicon gate C
2
MOS technology.
They have the same high speed performance of
LSTTL combined with true CMOS low power con-
sumption.
State changes of the counter are synchronous with
theLOW-to-HIGH transition of the Clock Pulse input.
Anasynchronous parallel load input overrides count-
ingandloadsthedatapresentontheDATAinputsinto
the flip-flops, which makes it possible to use the cir-
cuitsasprogrammable counters.Acountenable input
serves as the carry/borrow input in multi-stage
counters.
Control
input,
whether a circuitcounts up or down. AMAX/MINout-
putandaRippleClockoutputprovide overflow/under-
flow indication and make possible a variety of
methodsfor generating carry/borrow signals inmulti-
stagecounter applications.
Allinputs are equipped withprotection circuitsagainst
staticdischarge and transient excess voltage.
Down/Up, determines
1/14
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