參數(shù)資料
型號: M74HC166
廠商: 意法半導(dǎo)體
英文描述: 8 Bit PISO Shift Register(8位并行輸入串行輸出移位寄存器)
中文描述: 8位皮索移位寄存器(8位并行輸入串行輸出移位寄存器)
文件頁數(shù): 1/13頁
文件大小: 269K
代理商: M74HC166
M54HC166
M74HC166
October 1992
8 BIT PISO SHIFT REGISTER
B1R
(Plastic Package)
ORDER CODES :
M54HC166F1R
M74HC166B1R
M74HC166M1R
M74HC166C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Inter-
nal Con-
DESCRIPTION
The M54/74HC166 is a high speed C
2
MOS 8 BIT
PISO SHIFT REGISTER fabricated in silicon gate
C
2
MOStechnology.Ithas thesame highspeedper-
formance of LSTTL combined with true CMOS low
powerconsumption.
It consistsof parallel or serial inputs and a serial-out
8-bit shift register with gated clock inputs and an
overriding clear input. The parallel-in or serial-in
modes are controlled by the SHIFT/LOAD input.
WhentheSHIFT/LOAD inputis held high, the serial
data input isenabled andtheeightflip-flopsperform
serialshifting with each clock pulse. When heldlow,
the parallel data inputs are enabled and syn-
chronous loading occurs on the next clock pulse.
Clocking is accomplished on the low-to-high level
edge of the clock pulse. The CLOCK-INHIBIT input
should be changed to the high only while the
CLOCKinput is held high. A direct clear input over-
rides all other inputs, including the clock, and sets
all flip-flops to zero. Functional details are shown in
the truthtable and the timing chart.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
.
HIGH SPEED
f
MAX
= 57 MHz (TYP.) AT V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 4 mA (MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN AND FUNCTION COMPATIBLE WITH
54/74LS166
1/13
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