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參數(shù)資料
| 型號(hào)： | M68LC302CPU16VCT |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100 |
| 文件頁數(shù)： | 67/128頁 |
| 文件大小： | 641K |
| 代理商： | M68LC302CPU16VCT |
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ETHERNET Controller
4-4
MC68EN302 REFERENCE MANUAL
MOTOROLA
This read only field is the buffer descriptor number that was being accessed when a bus
error occurred. See 4.1.5 Interrupt Event Register (INTR_EVENT) for a description of the
bus error handling.
Bit 8—Reserved. Should be written to zero by the host processor. This bit is always read as
zero.
BDSIZE1-0—Buffer descriptor size. (R/W)
00 = 8 transmit buffer descriptors, 120 receive buffer descriptors
01 = 16 transmit buffer descriptors, 112 receive buffer descriptors
10 = 32 transmit buffer descriptors, 96 receive buffer descriptors
11 = 64 transmit buffer descriptors, 64 receive buffer descriptors
BDSIZE controls the allocation of the44 128 on-chip buffer descriptors between the
transmit and receive operations. Typical implementations will set BDSIZE(1–0) to 01
allowing 16 transmit buffer descriptors and 112 receive descriptors.
TSRLY—Transmit start early. (R/W)
TSRLY controls when the transmission of a frame will begin. Typical applications will set
TSRLY to 0.
0 = Frames do not begin transmitting until the transmit FIFO has only WMRK bytes
available (empty), where WMRK ranges from 96 to 120 bytes.
1 = The frame will begin transmitting after the WMRK number of bytes have been
written to the transmit FIFO where WMRK ranges from 8 to 32 bytes. This requires
low bus latency to avoid transmit FIFO underrun.
WMRK1–0—FIFO Watermark. (R/W)
00 = 8 FIFO bytes present or available
01 = 16 FIFO bytes present or available
10 = 24 FIFO bytes present or available
11 = 32 FIFO bytes present or available
The FIFO Watermark is used to control the start of a DMA burst. In the receive direction, the
DMA state machine waits for either an end-of-frame (EOF) or a WMRK number of bytes to
be in the receive FIFO prior to beginning a DMA burst of data out of the MC68EN302 to the
host bus. In the transmit direction, the DMA state machine waits for WMRK number of bytes
TSRLY
WMRK<1:0>
BYTES IN TRANSMIT FIFO AT
START OF TRANSMISSION
0
00
120
001
112
0
10
104
011
96
100
8
101
16
110
24
111
32
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