參數資料
型號: M68LC302CPU16VCT
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 4 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, PLASITC, LQFP-100
文件頁數: 24/128頁
文件大小: 641K
代理商: M68LC302CPU16VCT
MOTOROLA
MC68EN302 USER’S MANUAL
xiii
LIST OF TABLES
Table
Title
Page
Number
Table 1-1.
MC68EN302 Additional Registers.............................................................1-4
Table 2-1.
High Level Memory Map of MBC and MB Modules ..................................2-2
Table 2-2.
Module Bus Controller Register Set ..........................................................2-2
Table 2-3.
Pin Muxing Operation................................................................................2-3
Table 2-4.
DT Bit Encoding ........................................................................................2-5
Table 2-5.
Parity Pin Enable Operation ....................................................................2-12
Table 3-1.
DRAM Controller Registers ...................................................................... 3-1
Table 3-2.
Precharge Bit Encodings.......................................................................... 3-2
Table 3-3.
Wait State Bit Encodings.......................................................................... 3-2
Table 3-4.
Address Muxing Scheme ......................................................................... 3-7
Table 4-1.
Ethernet Controller Memory Map ..............................................................4-2
Table 4-2.
BD RAM Address Ranges.......................................................................4-18
Table 4-3.
Unicast Address Processing ...................................................................4-24
Table 4-4.
Broadcast and Multicast Address Processing .........................................4-24
Table 5-1.
MC68EN302 144-TQFP Pin/Signal Definition...........................................5-1
Table 5-2.
Pin Muxing Control ....................................................................................5-6
Table 5-3.
Address Muxing Scheme ........................................................................5-11
Table 7-1.
Boundary Scan Control Bits ......................................................................7-4
Table 7-2.
Boundary Scan Bit Definition.....................................................................7-6
Table 7-3.
Instruction Decoding................................................................................7-12
Table 8-1.
DRAM Interface Timing .............................................................................8-2
Table 8-2.
Ethernet Timing .........................................................................................8-5
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