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參數(shù)資料
| 型號(hào)： | M68HC11D3CFB1 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 1 MHz, MICROCONTROLLER, PQFP44 |
| 封裝： | QFP-44 |
| 文件頁數(shù)： | 38/124頁 |
| 文件大?。?/td> | 5398K |
| 代理商： | M68HC11D3CFB1 |
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PIN DESCRIPTIONS
2-8
TECHNICAL DATA
output port suitable for wired-OR operation. In wired-OR mode (a port C bit is at logic
level zero), it is actively driven low by the N-channel driver. When a port C bit is at logic
level one, the associated pin has high impedance, as neither the N- nor the P-channel
devices are active. It is customary to have an external pullup resistor on lines that are
driven by open-drain devices. Port C can only be configured for wired-OR operation
when the MCU is in single-chip mode. Refer to SECTION 6 PARALLEL I/O for addi-
tional information about port C functions.
2.10.4 Port D
Port D, an 8-bit, general-purpose I/O port has a data register (PORTD) and a data di-
rection register (DDRD). The eight port D bits (D[7:0]) can be used for general-purpose
I/O, for the serial communications interface (SCI) and serial peripheral interface (SPI)
subsystems, or for bus data direction control.
Port D can be read at any time and inputs return the sensed levels at the pin; whereas,
the outputs return the input level of the port D pin drivers. If PORTD is written, the data
is stored in an internal latch, and can be driven only if port D is configured for general-
purpose output. This port shares functions with the on-chip SCI and SPI subsystems,
while bits 6 and 7 control the direction of data flow on the bus in expanded and special
test modes.
Refer to SECTION 6 PARALLEL I/O.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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