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參數(shù)資料
| 型號： | M68AW512MN55ND6T |
| 廠商： | 意法半導體 |
| 英文描述： | 8 Mbit (512K x16) 3.0V Asynchronous SRAM |
| 中文描述： | 8兆位（為512k × 16）3.0V異步SRAM |
| 文件頁數(shù)： | 6/19頁 |
| 文件大?。?/td> | 296K |
| 代理商： | M68AW512MN55ND6T |
M68AW512M
6/19
OPERATION
The M68AW512M has a Chip Enable power down
feature which invokes an automatic standby mode
whenever either Chip Enable is de-asserted
(E = High) or LB and UB are de-asserted (LB and
UB = High). An Output Enable (G) signal provides
a high speed tri-state control, allowing fast read/
write cycles to be achieved with the common I/O
data bus. Operational modes are determined by
device control inputs W, E, LB and UB as summa-
rized in the Operating Modes table (see Table 2).
Read Mode
The M68AW512M is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, and Chip Enable (E) is asserted. This pro-
vides access to data from eight or sixteen, de-
pending on the status of the signal UB and LB, of
the 8,388,608 locations in the static memory array,
specified by the 19 address inputs. Valid data will
be available at the eight or sixteen output pins
within t
AVQV
after the last stable address, provid-
ing G is Low and E is Low. If Chip Enable or Output
Enable access times are not met, data access will
be measured from the limiting parameter (t
ELQV
,
t
GLQV
or t
BLQV
) rather than the address. Data out
may be indeterminate at t
ELQX
, t
GLQX
and t
BLQX
but data lines will always be valid at t
AVQV
.
Write Mode
The M68AW512M is in the Write mode whenever
the W and E are Low. Either the Chip Enable input
(E) or the Write Enable input (W) must be de-
asserted
during
Address
subsequent write cycles. When E (W) is Low, and
UB or LB is Low, write cycle begins on the W (E)'s
falling edge. When E and W are Low, and UB = LB
= High, write cycle begins on the first falling edge
of UB or LB. Therefore, address setup time is
referenced to Write Enable, Chip Enable or UB/LB
as t
AVWL
, t
AVEL
and t
AVBL
respectively, and is
determined by the latter occurring edge.
The Write cycle can be terminated by the earlier
rising edge of E, W or UB/LB.
If the Output is enabled (E = Low, G = Low, LB or
UB = Low), then W will return the outputs to high
impedance within t
WLQZ
of its falling edge. Care
must be taken to avoid bus contention in this type
of operation. Data input must be valid for t
DVWH
before the rising edge of Write Enable, or for t
DVEH
before the rising edge of E, or for t
DVBH
before the
rising edge of UB/LB whichever occurs first, and
remain valid for t
WHDX
, t
EHDX
and t
BHDX
respec-
tively.
transitions
for
Table 2. Operating Modes
Note: 1. X = V
IH
or V
IL
.
Operation
E
W
G
LB
UB
DQ0-DQ7
DQ8-DQ15
Power
Deselected
V
IH
X
X
X
X
Hi-Z
Hi-Z
Standby (I
SB
)
Deselected
X
X
X
V
IH
V
IH
Hi-Z
Hi-Z
Standby (I
SB
)
Lower Byte Read
V
IL
V
IH
V
IL
V
IL
V
IH
Data Output
Hi-Z
Active (I
CC
)
Lower Byte Write
IL
V
IL
X
V
IL
V
IH
Data Input
Hi-Z
Active (I
CC
)
Output Disabled
V
IL
V
IH
V
IH
X
X
Hi-Z
Hi-Z
Active (I
CC
)
Upper Byte Read
V
IL
V
IH
V
IL
V
IH
V
IL
Hi-Z
Data Output
Active (I
CC
)
Upper Byte Write
V
IL
V
IL
X
V
IH
V
IL
Hi-Z
Data Input
Active (I
CC
)
Word Read
V
IL
V
IH
V
IL
V
IL
V
IL
Data Output
Data Output
Active (I
CC
)
Word Write
V
IL
V
IL
X
V
IL
V
IL
Data Input
Data Input
Active (I
CC
)
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