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參數(shù)資料
| 型號： | M68AW256ML70ZB1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 4 Mbit (256K x16) 3.0V Asynchronous SRAM |
| 中文描述： | 4兆位（256K × 16）3.0V異步SRAM |
| 文件頁數(shù)： | 9/20頁 |
| 文件大小： | 161K |
| 代理商： | M68AW256ML70ZB1T |
9/20
M68AW256M
OPERATION
The M68AW256M has a Chip Enable power down
feature which invokes an automatic standby mode
whenever either Chip Enable is de-asserted
(E = High) or LB and UB are de-asserted (LB and
UB = High). An Output Enable (G) signal provides
a high speed tri-state control, allowing fast read/
write cycles to be achieved with the common I/O
data bus. Operational modes are determined by
device control inputs W, E, LB and UB as summa-
rized in the Operating Modes table (see Table 6).
Table 6. Operating Modes
Note: 1. X = V
IH
or V
IL
.
Read Mode
The M68AW256M is in the Read mode whenever
Write Enable (W) is High with Output Enable (G)
Low, and Chip Enable (E) is asserted. This pro-
vides access to data from eight or sixteen, de-
pending on the status of the signal UB and LB, of
the 4,194,304 locations in the static memory array,
specified by the 18 address inputs. Valid data will
be available at the eight or sixteen output pins
within t
AVQV
after the last stable address, provid-
ing G is Low and E is Low. If Chip Enable or Output
Enable access times are not met, data access will
be measured from the limiting parameter (t
ELQV
,
t
GLQV
or t
BLQV
) rather than the address. Data out
may be indeterminate at t
ELQX
, t
GLQX
and t
BLQX
but data lines will always be valid at t
AVQV
.
Figure 8. Address Controlled, Read Mode AC Waveforms
Note: E = Low, G = Low, W = High, UB = Low and/or LB = Low.
Operation
E
W
G
LB
UB
DQ0-DQ7
DQ8-DQ15
Power
Deselected
V
IH
X
X
X
X
Hi-Z
Hi-Z
Standby (I
SB
)
Deselected
X
X
X
V
IH
V
IH
Hi-Z
Hi-Z
Standby (I
SB
)
Lower Byte Read
V
IL
V
IH
V
IL
V
IL
V
IH
Data Output
Hi-Z
Active (I
CC
)
Lower Byte Write
V
IL
V
IL
X
V
IL
V
IH
Data Input
Hi-Z
Active (I
CC
)
Output Disabled
V
IL
V
IH
V
IH
X
X
Hi-Z
Hi-Z
Active (I
CC
)
Upper Byte Read
V
IL
V
IH
V
IL
V
IH
V
IL
Hi-Z
Data Output
Active (I
CC
)
Upper Byte Write
V
IL
V
IL
X
V
IH
V
IL
Hi-Z
Data Input
Active (I
CC
)
Word Read
V
IL
V
IH
V
IL
V
IL
V
IL
Data Output
Data Output
Active (I
CC
)
Word Write
V
IL
V
IL
X
V
IL
V
IL
Data Input
Data Input
Active (I
CC
)
AI03956
tAVAV
tAVQV
tAXQX
A0-A17
DQ0-DQ7 and/or DQ8-DQ15
VALID
DATA VALID
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