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參數(shù)資料
| 型號： | M68AF511AM70NC6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 4 Mbit (512K x8), 5V Asynchronous SRAM |
| 中文描述： | 4兆位（為512k × 8），5V的異步SRAM |
| 文件頁數(shù)： | 13/18頁 |
| 文件大?。?/td> | 129K |
| 代理商： | M68AF511AM70NC6T |
13/18
M68AF511A
Figure 12. Low V
CC
Data Retention AC Waveforms.
Table 9. Low V
CC
Data Retention Characteristics
Symbol
Parameter
Note: 1. All other Inputs at V
IH
≥
V
CC
–0.2V or V
IL
≤
0.2V.
2. Tested initially and after any design or process that may affect these parameteres.
t
AVAV
is Read cycle time.
3. No input may exceed V
CC
+0.2V.
Test Condition
Min
Typ
Max
Unit
I
CCDR(1)
Supply Current (Data Retention)
V
CC
= 2V, E
≥
V
CC
– 0.2V, f = 0
(3)
4.5
9
μA
t
CDR (1,2)
Chip Deselected to Data
Retention Time
0
ns
t
R(2)
Operation Recovery Time
t
AVAV
ns
V
DR (2)
Supply Voltage (Data Retention)
E
≥
V
CC
– 0.2V, f = 0
2
V
AI05915
DATA RETENTION MODE
tR
5.5V
tCDR
VCC 4.5V
VDR> 2.0V
E 2.2V
E
≥
VDR– 0.2V
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