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參數(shù)資料
| 型號： | M68AF511AM70NC6T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 4 Mbit (512K x8), 5V Asynchronous SRAM |
| 中文描述： | 4兆位（為512k × 8），5V的異步SRAM |
| 文件頁數(shù)： | 10/18頁 |
| 文件大小： | 129K |
| 代理商： | M68AF511AM70NC6T |
M68AF511A
10/18
Table 7. Read and Standby Mode AC Characteristics
Note: 1. Test conditions assume transition timig reference level = 0.3V
CC
or 0.7V
CC
.
2. At any given temperature and voltage condition, t
EHQZ
is less than t
ELQX
and t
GHQZ
is less than t
GLQX
for any given device.
3. These parameters are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
voltage levels.
4. Tested initially and after any design or process changes that may affect these parameters
Symbol
Parameter
M68AF511A
Unit
55
70
t
AVAV
Read Cycle Time
Min
55
70
ns
t
AVQV
Address Valid to Output Valid
Max
55
70
ns
t
AXQX(1)
Data hold from Address change
Min
5
5
ns
t
EHQZ(2,3)
Chip Enable High to Output Hi-Z
Max
20
25
ns
t
ELQV
Chip Enable Low to Output Valid
Max
55
70
ns
t
ELQX(1)
Chip Enable Low to Output Transition
Min
5
5
ns
t
GHQZ(2,3)
Output Enable High to Output Hi-Z
Max
20
25
ns
t
GLQV
Output Enable Low to Output Valid
Max
25
35
ns
t
GLQX(1)
Output Enable Low to Output Transition
Min
5
5
ns
t
PD(4)
Chip Enable High to Power Down
Max
0
0
ns
t
PU(4)
Chip Enable Low to Power Up
Min
55
70
ns
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