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參數(shù)資料
| 型號(hào)： | M66853J |
| 廠商： | Mitsubishi Electric Corporation |
| 元件分類： | FIFO |
| 英文描述： | SRAM TYPE FIFO MEMORY |
| 中文描述： | FIFO存儲(chǔ)器SRAM的類型 |
| 文件頁數(shù)： | 13/15頁 |
| 文件大?。?/td> | 118K |
| 代理商： | M66853J |
SRAM TYPE FIFO MEMORY
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
MITSUBISHI <DIGITAL ASSP>
Programmable Empty Flag Timing
t
CLKH
t
CLKL
t
ENS
t
PAE
n words in FIFO(1)
t
SKEW2
(2)
t
ENS
t
ENH
n+1 words in FIFO
t
ENH
t
PAE
(3)
WCLK
WEN1
RCLK
REN1
REN2
WEN2
(If Applicable)
PAE
t
ENS
t
ENH
NOTES :
1. PAF offset=m.
2. t
SKEW2
is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to change during that clock cycle.
If the time between the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW2
, then PAE may not change state
untill the next rising edge of RCLK.
3. If a read is performed on this rising edge of the read clock, there will be Empty+(n-1) words in the FIFO when PAE goes LOW.
13
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