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參數(shù)資料
| 型號： | M66853FP |
| 廠商： | Mitsubishi Electric Corporation |
| 元件分類： | FIFO |
| 英文描述： | SRAM TYPE FIFO MEMORY |
| 中文描述： | FIFO存儲器SRAM的類型 |
| 文件頁數(shù)： | 2/15頁 |
| 文件大?。?/td> | 118K |
| 代理商： | M66853FP |
SRAM TYPE FIFO MEMORY
M66850J/FP, M66851J/FP
M66852J/FP, M66853J/FP
MITSUBISHI <DIGITAL ASSP>
PIN and SIGNAL DESCRIPTIONS
V
CC
One+5 volt power supply pin.
GND
One 0 volt ground pin.
RS : Reset(INPUT)
When RS is set LOW, internal read and write pointers are set to
the first physical location,the output register is initialized to LOW,
FF and PAF are set HIGH, EF and PAE are set LOW.
A reset is required after power-up before a write operation.
WCLK : Write Clock(INPUT)
Data present on D0-D8 is written into the FIFO on the rising edge
of WCLK when the FIFO is enabled for writing.
RCLK : Read Clock(INPUT)
Data is read from the FIFO on the rising edge of RCLK when the
FIFO is enabled for reading.
WEN1 : Write Enable1(INPUT)
If the FIFO is configured to allow loading of the offset registers,
WEN1 is the only the write enable. When WEN1 is LOW, data on
D0-D8 is written to the FIFO on the rising edge of WCLK.
If the FIFO is configured to have two writeenables, data on D0-
D8 is written to the FIFO on the rising edge of WCLK when
WEN1 is LOW and WEN2 is High. But if the FF is LOW, data on
D0-D8 will not be written to the FIFO.
WEN2/LD : Write Enable2/Load(INPUT)
The function of this signal is defined at reset.
If WEN2/LD is HIGH at reset, this signal functions as a second
write enable(WEN2). If WEN2/LD is LOW at reset, this signal
functions as a control to load and read the offset register.
If the FIFO is configured to have two write enables, data on D0-
D8 is written to the FIFO on the rising edge of WCLK when
WEN1 is LOW and WEN2 is High. But if the FF is LOW, data on
D0-D8 will not be written to the FIFO.
If the FIFO is configured to have programmable flags, it is
possible to write and read from the offset registers. There are
four 9-bit offset registers. Two are used to control the
programmable Almost-Empty Flag
and
two are used to control the
programmable Almost-Full Flag.
Data on D0-D8 is written to an offset register on the rising edge
of WCLK when WEN1 is LOW and LD is LOW. Data on D0 – D8
is written to the offset registers in the following order :
PAE LSB, PAE MSB, PAF LSB, PAF MSB.
REN1, REN2 : Read Enable(INPUT)
Data is read from the FIFO and presented Q0-8 on the rising
edge of RCLK, when REN1 and REN2 are LOW and output port
is enabled.
If either Read Enable is HIGH,the output register holds the
previous data.
When the FIFO is empty, the Read Enable signals are ignored.
OE : Output Enable(INPUT)
When OE is LOW, the output port Q0-8 is enabled for output.
When OE is HIGH, the output port Q0-8 is placed in a high
impedance state.
D0-8 : Data Input(INPUT)
D0-8 is the 9-bit data input port.
Q0-8 : Data Output(OUTPUT)
Q0-8 is the 9-bit data Output port.
EF : Empty Flag(OUTPUT)
The Empty flag goes LOW when the read pointer is equal to the
write pointer.
When EF is LOW, the FIFO is empty and further data reads from
the data output are inhibited.
EF is synchronized to the rising edge of RCLK.
PAE : Programmable Almost-Empty Flag(OUTPUT)
When PAE is LOW, the FIFO is almost empty based on the
offset. The default offset is Empty+7. PAE is synchronized to the
rising edge of RCLK.
FF : Full Flag(OUTPUT)
When FF is LOW, the FIFO is full and further data writes into the
data input are inhibited.
The Full Flag goes LOW when the FIFO is full of data.
FF is synchronized to the rising edge of WCLK.
PAF : Programmable Almost-Full Flag(OUTPUT)
When PAF is LOW, the FIFO is almost full based on the offset.
The default offset is Full-7. PAF is synchronized to the rising
edge of WCLK.
2
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PDF描述 |
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| M66853J | SRAM TYPE FIFO MEMORY |
| M67706U | 896-941MHz,7.5V,4W,FM PORTABLE RADIO |
| M67706 | 806-870MHz,7.5V,4W,FM PORTABLE RADIO |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M66853J | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SRAM TYPE FIFO MEMORY |
| M66CE-12 | 制造商:MCLENNAN 功能描述:MOTOR SERVO 12V DC |
| M66CE-24 | 制造商:MCLENNAN 功能描述:MOTOR SERVO 24V DC 制造商:MCLENNAN 功能描述:MOTOR, SERVO, 24V DC 制造商:MCLENNAN 功能描述:MOTOR, SERVO, 24V DC; SVHC:No SVHC (19-Dec-2012); Current Rating:65mA; External Diameter:66mm; External Length / Height:64mm; Fixing Hole Diameter:4mm; Inertia:214g-cm2; No Load Speed:2900rpm; Nom Operating Voltage:24VDC; Operating ;RoHS Compliant: Yes |
| M66CI500T | 制造商:MCLENNAN SERVO SUPPLIES 功能描述:24VDC SERVO MOTOR+ENCODER |
| M66T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TO-92 MELODY TRANSISTOR TYPE |
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