參數(shù)資料
型號: M66236FP
廠商: Mitsubishi Electric Corporation
英文描述: STANDARD CLOCK GENERATOR
中文描述: 標(biāo)準(zhǔn)時鐘發(fā)生器
文件頁數(shù): 1/5頁
文件大?。?/td> 57K
代理商: M66236FP
1
M66236FP
STSTANDARD CLOCK GENERATOR
V
CC
TEST3
GND
TR
V
CC
CKO
CKO
CNTCK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DESCRIPTION
M66236 is produced using the silicon gate CMOS process. It
is able to output clock input signal in sync with optional exter-
nal trigger input signal.
It features excellent synchronizing precision (jitter) over a
wide frequency band range.
FEATURES
5V single power supply (5V
±
5%)
Frequency band: 12 ~ 25MHz
Synchronizing precision (jitter):
±
5ns
Output types
(1) Output of the same frequency as input clock, and its in-
version
(2) 1/2 divider clock output and its inversion
(3) One-shot pulse output
(4) Continuous clock output
Noise in the positive direction to trigger input is removed by
built-in noise killer circuit
APPLICATION
Clock phase control for horizontal synchronization
PIN CONFIGURATION (TOP VIEW)
BLOCK DIAGRAM
MIMITSUBISHI
DIDIGITAL ASSP
Note: Keep test pins (TEST 1 to 3) open.
Outline 16P2N-A
M
GND
CKO
SYNC CLOCK
OUTPUT
SYNC CLOCK
INVERTED OUTPUT
CKO/2CLOCK OUTPUT
1/2 DIVIDER SYNC
CLOCK INVERTED OUTPUT
CNTCKCLOCK OUTPUT
PULSEPULSE OUTPUT
CKO
7
CKO/2
6
9
4
1
2
3
15
12
16
TEST2 TEST OUTPUT
TEST3 TEST OUTPUT
14
8
5
GND
GND
TEST1
TEST
INPUT
TR
TRIGGER
INPUT
CLK IN
CLOCK
INPUT
V
CC
V
CC
13
SYNC CLOCK SELECTOR CIRCUIT
DELAY CLOCK
GENERATION CIRCUIT
PHASE DETECTION CIRCUIT
S
TEST OUTPUT
TRIGGER INPUT
SYNC CLOCK OUTPUT
SYNC CLOCK
CLOCK INPUT
TEST INPUT
TEST OUTPUT
ONE-SHOOUTPUT
1/2 DIINVERTED OUTPUT
1/CLOCK OUTPUT
CLK IN
TEST1
TEST2
PULSE
GND
CKO/2
CKO/2
GND
11
10
相關(guān)PDF資料
PDF描述
M66238FP STANDARD CLOCK GENERATOR WITH PLL FREQUENCY SYNTHESIZER
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