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參數(shù)資料
| 型號： | M66014FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 16-BIT SERIAL BUS CONTROLLER |
| 中文描述： | 16位串行總線控制器 |
| 文件頁數(shù)： | 2/2頁 |
| 文件大?。?/td> | 34K |
| 代理商： | M66014FP |
2
MITSUBISHI
DIGITAL ASSP
M66014FP
16-BIT SERIAL BUS CONTROLLER
3.
Serial data input/output operation
A cycle of 16-bit serial output data setting and serial data
communication starts with a write access given by micro-
computer to transmission shift registers in M66014.
M66014 has two 8-bit shift registers, on for upper byte
(SR
U
), the other for lower byte (SR
L
). If the CS status rises
from “L” to “H” after a write access is given to SR
L
, serial
data communication is started. SR
U
8-bit data and SR
L
8-
bit data are output in series in this order. Output of each
data starts from its most significant bit.
At the CS rise edge, busy flag in M66014 is set, and OE
output shifts from “H” to “L”. Shift clock SCLK and serial
data SOUT are then output.
At SCLK fall edges, serial output shift register executes
shifting operation, and data on shift register is output in se-
ries from pin SOUT. Serial input data from pin SIN is taken
into input shift register at SCLK rise edges.
After the SCLK 16T rise edge, the status of SOUT and OE
shifts to “H” after one bit’s delay of SCLK, and busy flag is
reset. When interrupt output is being set to enable, INT
output is set.
(Remarks)
(1)If CS rises after write operation is executed on SR
L
only
and not on SR
U
, SR
U
data is unstable.
(2)When write operations executed on SR
L
, M66014 be-
comes ready for start of serial communication and stands
by for detection of CS rise. However, if a read access is
given after data is written on SR
L
while CS is maintained
on “L” level, this standby status is canceled. To resume se-
rial communication in this case, rewrite data on SR
L
and
raise CS.
CS
Serial communication period
SRL
write operation
OE
INT
SCLK
SOUT
SIN
Busy flag
(in M66014)
Serial Communication Timing Chart
D0
15
D0
14
D0
13
D0
12
D0
11
D0
10
D0
9
D0
8
D0
7
D0
6
D0
5
D0
4
D0
3
D0
2
D0
1
D0
0
(D7
U
)
(D0
U
) (D7
L
)
(D0
L
)
DI
8
DI
7
DI
6
DI
5
DI
4
DI
3
DI
2
DI
1
DI
0
1T
2T
8T
9T
16T
DI
15
DI
14
DI
13
DI
12
DI
11
DI
10
DI
9
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|---|---|
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