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參數(shù)資料
| 型號： | M63850P |
| 元件分類： | JFETs |
| 英文描述： | 1.5 A, 3 CHANNEL, N AND P-CHANNEL, Si, POWER, MOSFET |
| 文件頁數(shù)： | 1/5頁 |
| 文件大小： | 49K |
| 代理商： | M63850P |
Apr. 2005
PIN CONFIGURATION
MITSUBISHI SEMICONDUCTOR <TRANSISTOR ARRAY>
M63850P/FP
4-UNIT 1.5A DMOS ARRAY WITH CLAMP DIODE
DESCRIPTION
The M63850P/FP is a inverter input power DMOS transistor
array that consists of 4 independent output N-channel
DMOS transistors.
FEATURES
4 circuits of N-channels DMOS
High breakdown voltage (VDS
≥ 80V)
High-current driving (IDS(max) = 1.5A)
With clamping diodes
Drain-source on-state low resistance
(RON = 0.72
, @ = 1.25A)
Wide operating temperature range (Ta = –40 to +85
°C)
APPLICATION
Drives of relays and printers, digit drives of indication ele-
ments (LEDs and lamps)
FUNCTION
The M63850P/FP is consists of 4 independent N-channel
DMOS transistors. Each DMOS transistor is connected in a
common-source with GND PIN. The clamp diodes for spike
killers are connected between the output pin and the COM
pin of each DMOS transistor. The maximum of Drain current
is 1.5A. The maximum Drain-Source voltage is 80V.
CIRCUIT DIAGRAM
V
A
V
A
W
°C
7
–0.5 ~ +80
1.5
–0.5 ~ VDD
80
1.5
1.47(P)/1.00(FP)
–40 ~ +85
–55 ~ +125
Ratings
Unit
Symbol
Parameter
Conditions
Supply voltage
Drain-source voltage
Drain current
Input voltage
Clamping diode reverse voltage
Clamping diode forward current
Power dissipation
Operating temperature
Storage temperature
Output, H
Current per circuit output, L
Ta = 25
°C, when mounted on board
VDD
VDS
IDS
VI
VR
IF
Pd
Topr
Tstg
ABSOLUTE MAXIMUM RATINGS (Unless otherwise noted, Ta = –40 ~ +85
°C)
PRELIMINARY
Notice:
This
is not
a final
specification.
Some
param
etric lim
its are
subject
to change.
30k
4.2k
COM
VDD
OUTPUT
GND
INPUT
The four circuits share the COM and GND.
The diode, indicated with the dotted line, is parasitic, and
cannot be used.
Unit :
16P4(P)
16P2N(FP)
NC : No connection
Package type
1
O1
←
IN1
→
IN2
→
NC
COM
→O4
O2
←
COM
GND
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
→O3
←IN3
VDD
←IN4
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