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參數(shù)資料
| 型號： | M5M5V5636GP16 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM |
| 中文描述： | 18874368位（524288 - Word的36位）網(wǎng)絡(luò)的SRAM |
| 文件頁數(shù)： | 1/17頁 |
| 文件大?。?/td> | 269K |
| 代理商： | M5M5V5636GP16 |
MITSUBISHI LSIs
M5M5V5636GP –16
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
1
MITSUBISHI
ELECTRIC
Advanced Information
M5M5V5636GP REV.0.1
DESCRIPTION
The M5M5V5636GP is a family of 18M bit synchronous SRAMs
organized as 524288-words by 36-bit. It is designed to eliminate
dead bus cycles when turning the bus around between reads and
writes, or writes and reads. Mitsubishi's SRAMs are fabricated
with high performance, low power CMOS technology, providing
greater reliability. M5M5V5636GP operates on 3.3V power/ 2.5V
I/O supply or a single 3.3V power supply and are 3.3V CMOS
compatible.
FEATURES
Fully registered inputs and outputs for pipelined operation
Fast clock speed: 167 MHz
Fast access time: 3.8 ns
Single 3.3V -5% and +5% power supply V
DD
Separate V
DDQ
for 3.3V or 2.5V I/O
Individual byte write (BWa# - BWd#) controls may be tied
LOW
Single Read/Write control pin (W#)
CKE# pin to enable clock and suspend operations
Internally self-timed, registers outputs eliminate the need to
control G#
Snooze mode (ZZ) for power down
Linear or Interleaved Burst Modes
Three chip enables for simple depth expansion
Package
100pin TQFP
APPLICATION
High-end networking products that require high bandwidth, such
as switches and routers
.
FUNCTION
Synchronous circuitry allows for precise cycle control
triggered by a positive edge clock transition.
Synchronous signals include : all Addresses, all Data Inputs, all
Chip Enables (E1#, E2, E3#), Address Advance/Load (ADV),
Clock Enable (CKE#), Byte Write Enables (BWa#, BWb#, BWc#,
BWd#) and Read/Write (W#). Write operations are controlled by
the four Byte Write Enables (BWa# - BWd#) and Read/Write(W#)
inputs. All writes are conducted with on-chip synchronous self-
timed write circuitry.
Asynchronous inputs include Output Enable (G#), Clock (CLK)
and Snooze Enable (ZZ). The HIGH input of ZZ pin puts the
SRAM in the power-down state.The Linear Burst order (LBO#) is
DC operated pin. LBO# pin will allow the choice of either an
interleaved burst, or a linear burst.
All read, write and deselect cycles are initiated by the ADV
LOW input. Subsequent burst address can be internally
generated as controlled by the ADV HIGH input.
PART NAME TABLE
Part Name
Frequency
Access
Cycle
Active Current
(max.)
Standby Current
(max.)
M5M5V5636GP - 16
167MHz
3.8ns
6.0ns
340mA
20mA
2001.July Rev.0.1
Advanced Information
Notice: This is not final specification.
Some parametric limits are subject to change.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M5V5636GP-16 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM |
| M5M5V5636GP-16_03 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM |
| M5M5V5636GP-16I | 制造商:Renesas Electronics Corporation 功能描述: |
| M5M5V5636GP-20 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM |
| M5M5V5636GP-22 | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM |
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