參數(shù)資料
型號(hào): M5M4V64S40ATP-8
廠商: Mitsubishi Electric Corporation
英文描述: 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
中文描述: 64M號(hào)(4銀行甲1048576字x 16位)同步DRAM
文件頁(yè)數(shù): 23/51頁(yè)
文件大小: 1084K
代理商: M5M4V64S40ATP-8
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.1.3)
Mar'98
M5M4V64S40ATP-8A,-8L,-8, -10L, -10
64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of
the same bank
. Random column access is al-
lowed. Write recovery time (tWR) is required from the last data to PRE command.
Write Interrupted by Precharge (BL=4)
CLK
Command
A0-9
A10
BA0,1
DQ
Write
Yi
0
00
PRE
0
00
DQM
ACT
Xb
Xb
00
tWR
tRP
A11
Xb
Dai0
Dai1
Dai2
23
[ Write Interrupted by Burst Terminate ]
A burst terminate command TBST can be used to terminate a burst write operation. In this case,
the write recovery time is not required and the bank remains active (Please see the waveforms
below). The WRITE to TBST minimum interval is one CLK.
Write Interrupted by Burst Terminate(BL=4)
CLK
Command
A0-9
A10
BA
DQ
WRITE
Yi
0
0
Dai0
DQMU/DQML
(DQM)
TBST
Dai1
Dai2
相關(guān)PDF資料
PDF描述
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M5M4V64S40ATP-8L 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM
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