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參數(shù)資料
| 型號： | M5M4V64S20ATP-12 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| 中文描述： | 64M號（4銀行甲4194304字× 4位）同步DRAM |
| 文件頁數(shù)： | 22/48頁 |
| 文件大?。?/td> | 1097K |
| 代理商： | M5M4V64S20ATP-12 |
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M5M4V64S20ATP-8, -10, -12
Jan'97
Preliminary
MITSUBISHI LSIs
64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM
MITSUBISHI ELECTRIC
SDRAM (Rev.0.2)
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H) command.
The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 64Mbit memory cells.
The auto-refresh is performed on 4 banks concurrently. Before performing an auto-refresh, all banks must
be in the idle state. Auto-refresh to auto-refresh interval is minimum tRC. Any command must not be
supplied to the device before tRC from the REFA command.
Auto-Refresh
CLK
/CS
/RAS
/CAS
/WE
CKE
A0-11
BA0,1
Auto Refresh on All Banks
minimum tRC
NOP or DESELECT
Auto Refresh on All Banks
22
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| M5M4V64S20ATP-8 | 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-8A | 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-8L | 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M51008KR-10L | 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M5M4V64S20ATP-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-8A | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-8L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S30ATP-10 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM |
| M5M4V64S30ATP-10L | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:64M (4-BANK x 2097152-WORD x 8-BIT) Synchronous DRAM |
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