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參數(shù)資料
| 型號： | M5M4V16G50DFP-10 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM |
| 中文描述： | 1,600（2 -銀行甲262144字× 32位）同步圖形RAM |
| 文件頁數(shù)： | 4/33頁 |
| 文件大小： | 167K |
| 代理商： | M5M4V16G50DFP-10 |
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M5M4V16G50DFP -8, -10, -12
Jan'97
Preliminary
MITSUBISHI LSIs
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0)
PIN FUNCTION
CLK
Input
Master Clock: All other inputs are referenced to the rising edge of CLK.
CKE
Input
Clock Enable: CKE controls internal clock. When CKE is low, internal clock
for the following cycle is stopped. CKE is also used to select auto / self
refresh. After self refresh mode is started, CKE becomes asynchronous
input. Self refresh is maintained as long as CKE is low.
/CS
Input
Chip Select: When /CS is high, any command means No Operation.
/RAS, /CAS, /
WE, and DSF
Input
Combination of /RAS, /CAS, /WE, and DSF defines basic commands.
A0-9
Input
A0-9 specify the Row / Column Address in conjunction with BA. The Row
Address is specified by A0-9. The Column Address is specified by A0-7.
A9 is also used to indicate precharge option. When A9 is high at a read /
write command, an auto precharge is performed. When A9 is high at a
precharge command, both banks are precharged.
A10
Input
Bank Address: A10 (BA) specifies the bank to which a
command is applied. A10 (BA) must be set with ACT, PRE, READ,
WRITE commands.
DQ0-31
Input / Output
Data In/Data out are referenced to the rising edge of CLK. These pins
are used for input mask pins for Write-Per-Bit and column/byte mask
inputs for Block Writes.
Input/Output Byte Mask: When DQM0-3 are high during a write, data for
the current cycle is masked. When DQM0-3 are high during a read,
output data is disabled at the next cycle.
DQM0 controls byte 0 (DQ7-0), DQM1 controls byte 1 (DQ15-8), DQM2
controls byte 2 (DQ23-16), and DQM3 controls byte 3 (DQ31-24).
DQM0 -
DQM3
Input
VREF
Input
Reference voltage for all inputs.
Vdd, Vss
Power Supply
Power Supply for the memory array and peripheral circuitry.
VddQ, VssQ
Power Supply
VddQ and VssQ are supplied to the Output Buffers only.
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|---|---|
| M5M4V16G50DFP-12 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM |
| M5M4V16G50DFP-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM |
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