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參數(shù)資料
| 型號： | M5M4V16G50DFP-10 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM |
| 中文描述： | 1,600（2 -銀行甲262144字× 32位）同步圖形RAM |
| 文件頁數(shù)： | 20/33頁 |
| 文件大?。?/td> | 167K |
| 代理商： | M5M4V16G50DFP-10 |
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M5M4V16G50DFP -8, -10, -12
Jan'97
Preliminary
MITSUBISHI LSIs
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0)
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set in the same
cycle as the WRITE. The following (BL -1) data is written into the RAM, when the Burst Length is BL.
The start address is specified by A7-0, and the address sequence of burst data is defined by the Burst Type.
A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be hidden
behind continuous output data (in case of BL=4) by interleaving the dual banks. When A9 is high at a
WRITE command, the auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE,
ACT) to the same bank is inhibited until the internal precharge is complete. The internal precharge begins
at tWR after the last input datacycle. The next ACT command can be issued after tRP from the internal
precharge timing.
Dual Bank Interleaving WRITE (BL=4)
CLK
Command
A0-8
A9
A10
DQ
ACT
Xa
Xa
0
Write
Y
0
0
Write
Y
0
1
Da0
Da1
Da2
Da3
ACT
Xb
Xb
1
PRE
0
0
tRCD
Burst Length
Db0
Db1
Db2
Db3
tRCD
tWR
WRITE with Auto-Precharge (BL=4)
CLK
Command
A0-8
A9
A10
DQ
ACT
Xa
Xa
0
Write
Y
1
0
Da0
Da1
Da2
Da3
ACT
Xa
Xa
0
Internal precharge begins
tRCD
tRP
tWR
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| M5M4V16G50DFP-12 | 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M4V16G50DFP-12 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM |
| M5M4V16G50DFP-8 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM |
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