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參數(shù)資料
| 型號(hào)： | M5M467405DTP-5 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM |
| 中文描述： | 江戶模式67108864位（16777216 - Word的4位）動(dòng)態(tài)隨機(jī)存儲(chǔ)器 |
| 文件頁數(shù)： | 13/39頁 |
| 文件大小： | 403K |
| 代理商： | M5M467405DTP-5 |
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MITSUBISHI
ELECTRIC
Jun. 1999
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
MITSUBISHI LSIs
(Rev. 1.1)
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
13
ELECTRICAL CHARACTERISTICS
(Ta=0 70 , Vcc=3.3V 0.3V, Vss=0V, unless otherwise noted)
(Note 2)
C
Symbol
Parameter
Limits
Parameter
Symbol
M5M46X405B-5S
M5M46X805B-5S
M5M465165B-5S
M5M46X405B-6S
M5M46X805B-6S
M5M465165B-6S
Unit
Min
100
84
Max
Self Refresh RAS low pulse width
Self Refresh RAS high precharge time
t
RASS
Min
100
104
Max
μS
ns
ns
t
RPS
t
CHS
- 50
- 50
Self Refresh CAS hold time
SELF REFRESH SPECIFICATIONS
BURST REFRESH
< 128 ms >
BURST REFRESH
< 128 ms >
t
NS
t
SN
DISTRIBUTED REFRESH
< 128 ms >
DISTRIBUTED REFRESH
< 128 ms >
t
NS
t
SN
(1) In case of CBR distributed refresh
SELF REFRESH ENTRY & EXIT CONDITIONS
The last / first full refresh cycles must be made within tNS / tSN before / after self refresh ,
on the condition of tNS 128 ms and tSN 128 ms.
(2) In case of burst refresh
The last / first full refresh cycles must be made within tNS / tSN before / after self refresh ,
on the condition of tNS 16 ms and tSN 16 ms.
Self refresh devices are denoted by "S" after speed item, like -5S / -6S . The other characteristics
and requirements than the below are same as normal devices.
C
(Ta=0 70 , Vcc=3.3V 0.3V, Vss=0V, unless otherwise noted See notes 14,15)
TIMING REQUIREMENTS
Self refresh period
Self refresh period
I
CC8 (AV)
Average supply current
from Vcc
Extended - Refresh cycle
(note 5,6)
I
CC9 (AV)
Average supply current
from Vcc
Self - Refresh cycle
(note 6)
Limits
Typ
Min
Max
Unit
Test conditions
CAS before RAS refresh cycling
input high level Vcc-0.2V
input low level 0.2V
output = OPEN , tRC = 31.25
μs
tRAS = tRAS(min)
500
μA
RAS = CAS 0.2V
output = OPEN
400
μA
300ns
M5M46X405B-5S,6S
M5M46X805B-5S,6S
M5M465165B-5S,6S
M5M46X405B-5S,6S
M5M46X805B-5S,6S
M5M465165B-5S,6S
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M5M467405DTP-5S | EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM |
| M5M467405DTP-6 | EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM |
| M5M467405DTP-6S | EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM |
| M5M465800BTP-5S | FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM |
| M5M465400BJ-5 | FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M467405DTP-5S | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM |
| M5M467405DTP-6 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM |
| M5M467405DTP-6S | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM |
| M5M467800BJ | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM |
| M5M467800BJ-5 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM |
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