參數(shù)資料
型號: M5M467405DTP-5
廠商: Mitsubishi Electric Corporation
英文描述: EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
中文描述: 江戶模式67108864位(16777216 - Word的4位)動態(tài)隨機存儲器
文件頁數(shù): 10/39頁
文件大?。?/td> 403K
代理商: M5M467405DTP-5
MITSUBISHI
ELECTRIC
Jun. 1999
EDO MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
EDO MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
MITSUBISHI LSIs
(Rev. 1.1)
M5M467405/465405BJ,BTP -5,-6,-5S,-6S
M5M467805/465805BJ,BTP -5,-6,-5S,-6S
M5M465165BJ,BTP -5,-6,-5S,-6S
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and EDO Mode Cycles)
(Ta=0 70 , Vcc=3.3 0.3V, Vss=0V, unless otherwise noted See notes 14,15)
C
Read and Refresh Cycles
Parameter
Symbol
Limits
Unit
Note 22: Either t
RCH
or t
RRH
must be satisfied for a read cycle.
Read cycle time
RAS low pulse width
CAS low pulse width
t
RC
t
RAS
t
CAS
0
t
CSH
t
RSH
t
RCS
CAS hold time after RAS low
RAS hold time after CAS low
Read Setup time before CAS low
Read hold time after CAS high
Read hold time after RAS high
(Note 22)
(Note 22)
t
RCH
t
RRH
t
RAL
t
CAL
0
t
ORH
Column address to RAS hold time
Column address to CAS hold time
RAS hold time after OE low
10000
10000
10000
10000
84
50
8
35
13
0
25
13
13
0
0
104
60
10
40
15
0
30
18
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
Max
Min
Max
t
OCH
13
15
ns
CAS hold time after OE low
Note 14: The timing requirements are assumed t
T
=2ns.
15: V
IH(min)
and V
IL(max)
are reference levels for measuring timing of input signals.
16: t
RCD(max)
is specified as a reference point only. If t
RCD
is less than t
RCD(max),
access time is t
RAC.
If t
RCD
is greater than t
RCD(max),
access
time is controlled exclusively by t
CAC
or t
AA.
17: t
RAD(max)
is specified as a reference point only. If t
RAD
t
RAD(max)
and t
ASC
t
ASC(max),
access time is controlled exclusively by t
AA.
18: t
ASC(max)
is specified as a reference point only. If t
RCD
t
RCD(max)
and t
ASC
t
ASC(max),
access time is controlled exclusively by t
CAC.
19:
Either t
DZC
or t
DZO
must be satisfied.
20: Either t
RDD
or
t
CDD
or t
ODD
or t
WED
must be satisfied.
21: t
T
is measured between V
IH(min)
and V
IL(max).
Parameter
Symbol
Limits
Unit
M5M46X405B-5,5S
M5M46X805B-5,5S
M5M465165B-5,5S
Min
M5M46X405B-6,6S
M5M46X805B-6,6S
M5M465165B-6,6S
Min
Refresh cycle time
t
REF
64
64
128
ms
ms
Max
Max
RAS high pulse width
Delay time, RAS low to CAS low
t
RP
t
RCD
t
CRP
t
RPC
t
CPN
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
(Note21)
(Note16)
(Note17)
(Note18)
45
30
0
40
14
13
50
5
10
12
10
10
0
0
1
37
25
0
30
14
5
10
50
8
10
8
8
0
0
1
t
RAD
t
ASR
t
ASC
t
RAH
t
CAH
t
DZC
t
T
Column address delay time from RAS low
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
Column address hold time after CAS low
Transition time
(Note19)
(Note19)
(Note20)
(Note20)
(Note20)
Delay time, data to CAS low
Delay time, data to OE low
Delay time, RAS high to data
Delay time, CAS high to data
Delay time, OE high to data
Delay time, W low to data
t
DZO
t
RDD
t
CDD
t
ODD
t
WED
0
0
0
0
15
13
15
13
15
13
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
128
Refresh cycle time (S-version only)
t
REF
ns
ns
ns
ns
ns
ns
15
13
(Note20)
10
M5M46X405B-5,5S
M5M46X805B-5,5S
M5M465165B-5,5S
M5M46X405B-6,6S
M5M46X805B-6,6S
M5M465165B-6,6S
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