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參數資料
| 型號： | M5LV-128/68-15YI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | Fifth Generation MACH Architecture |
| 中文描述： | EE PLD, 15 ns, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數： | 8/47頁 |
| 文件大小： | 1145K |
| 代理商： | M5LV-128/68-15YI |
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16
MACH 5 Family
BLOCK DIAGRAM — M5(LV)-256/XXX
Macrocells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Control
Generator
64
PT
2
PT
OE
I/O
Cells
16
32
7
PT
7
2
32
16
Macrocells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Control
Generator
64
PT
2
PT
OE
I/O
Cells
16
32
7
PT
7
2
32
16
Macrocells
Control
Generator
64
PT
2
PT
OE
16
32
7
PT
7
2
32
16
I/O
Cells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Macrocells
Control
Generator
64
PT
2
PT
OE
16
32
7
PT
7
2
32
16
I/O
Cells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Block
A/Macrocells
0-15
Block
D/Macrocells
0-15
Block
B/Macrocells
0-15
Block
C/Macrocells
0-15
Block
Interconnect
Macrocells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Control
Generator
64
PT
2
PT
OE
I/O
Cells
16
32
7
PT
7
2
32
16
Macrocells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Control
Generator
64
PT
2
PT
OE
I/O
Cells
16
32
7
PT
7
2
32
16
Macrocells
Control
Generator
64
PT
2
PT
OE
16
32
7
PT
7
2
32
16
I/O
Cells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Macrocells
Control
Generator
64
PT
2
PT
OE
16
32
7
PT
7
2
32
16
I/O
Cells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Block
A/Macrocells
0-15
Block
D/Macrocells
0-15
Block
B/Macrocells
0-15
Block
C/Macrocells
0-15
Block
Interconnect
Macrocells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Control
Generator
64
PT
2
PT
OE
I/O
Cells
16
32
7
PT
7
2
32
16
Macrocells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Control
Generator
64
PT
2
PT
OE
I/O
Cells
16
32
7
PT
7
2
32
16
Macrocells
Control
Generator
64
PT
2
PT
OE
16
32
7
PT
7
2
32
16
I/O
Cells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Macrocells
Control
Generator
64
PT
2
PT
OE
16
32
7
PT
7
2
32
16
I/O
Cells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Block
A/Macrocells
0-15
Block
D/Macrocells
0-15
Block
B/Macrocells
0-15
Block
C/Macrocells
0-15
Block
Interconnect
Macrocells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Control
Generator
64
PT
2
PT
OE
I/O
Cells
16
32
7
PT
7
2
32
16
Macrocells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Control
Generator
64
PT
2
PT
OE
I/O
Cells
16
32
7
PT
7
2
32
16
Macrocells
Control
Generator
64
PT
2
PT
OE
16
32
7
PT
7
2
32
16
I/O
Cells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Macrocells
Control
Generator
64
PT
2
PT
OE
16
32
7
PT
7
2
32
16
I/O
Cells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Block
A/Macrocells
0-15
Block
D/Macrocells
0-15
Block
B/Macrocells
0-15
Block
C/Macrocells
0-15
Block
Interconnect
S
E
G
M
E
N
T
I
N
T
E
R
C
O
N
E
C
T
CLK0
CLK1
CLK2
CLK3
4
SEGMENT
0
SEGMENT
3
SEGMENT
2
SEGMENT
1
I 0
I 3
I 1
I 2
20446G-009
相關PDF資料 |
PDF描述 |
|---|---|
| M5LV-128/68-5YC | Fifth Generation MACH Architecture |
| M5LV-384/160-6HC | Fifth Generation MACH Architecture |
| M5LV-384/160-7HC | Fifth Generation MACH Architecture |
| M5LV-384/184-10HC | Fifth Generation MACH Architecture |
| M5LV-384/184-10HI | Fifth Generation MACH Architecture |
相關代理商/技術參數 |
參數描述 |
|---|---|
| M5LV-256/104-10AC | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10AI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10HC | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10HI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10VC | 功能描述:CPLD - 復雜可編程邏輯器件 PROGRAM HI DENSITY CPLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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