參數(shù)資料
型號： M5LV-128/68-15YI
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： PLD
英文描述： Fifth Generation MACH Architecture
中文描述： EE PLD, 15 ns, PQFP100
封裝： PLASTIC, QFP-100
文件頁數(shù)： 44/47頁
文件大?。?/td> 1145K
代理商： M5LV-128/68-15YI
6
MACH 5 Family
Macrocells
The macrocells for MACH 5 devices consist of a storage element which can be congured for
combinatorial, registered or latched operation (Figure 3). The D-type ip-ops can be congured
as T-type, J-K, or S-R operation through the use of the XOR gate associated with each macrocell.
Each PAL block has the capability to provide two input registers by using macrocells 0 and 15. In
order to use this option, these macrocells must be accessed via the I/O pins associated with
macrocells 3 and 12, respectively. Once the macrocell is used as an input register, it cannot be used
for logic, so its clusters can be re-directed through the logic allocator to another macrocell. The
I/O pins associated with macrocells 0 and 15 can still be used as input pins. Although the I/O pins
for macrocells 3 and 12 are used to connect to the input registers, these macrocells can still be
used as “buried” macrocells to drive device logic via the matrix.
Control Generator
The control generator provides four congurable clock lines and three congurable set/reset lines to
each macrocell in a PAL block. Any of the four clock lines and any of the three set/reset lines can
be independently selected by any ip-op within a block. The clock lines can be congured to
provide synchronous global (pin) clocks and asynchronous product term clocks, sum term clocks,
and latch enables (Figure 4). Three of the four global clocks, as well as two product-term clocks
and one sum-term clock, are available per PAL block. Positive or negative edge clocking is
available as well as advanced clocking features such as
complementary and biphase clocking.
Complementary clocking provides two clock lines exactly 180 degrees out of phase, and is useful
in applications such as fast data paths. A biphase clock line clocks ip-ops on both the positive
and negative edges of the clock. The conguration options for the four clock lines per PAL block
are as follows:
Clock Line 0 Options
x
Global clock (0, 1, 2, or 3) with positive or negative edge clock enable
x
Product-term clock (A*B*C)
x
Sum-term clock (A+B+C)
Logic
Allocator
5-8
Clusters/
MC
Prog. Polarity
Mode
Selection
Control
Bus
Macrocell
D
Q
20446G-003
Figure 3. Macrocell Diagram
相關(guān)PDF資料
PDF描述
M5LV-128/68-5YC Fifth Generation MACH Architecture
M5LV-384/160-6HC Fifth Generation MACH Architecture
M5LV-384/160-7HC Fifth Generation MACH Architecture
M5LV-384/184-10HC Fifth Generation MACH Architecture
M5LV-384/184-10HI Fifth Generation MACH Architecture
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M5LV-256/104-10AC 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10AI 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10HC 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10HI 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10VC 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM HI DENSITY CPLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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