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參數(shù)資料
| 型號： | M59DR008EN |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
| 中文描述： | 8兆位512KB的x16插槽，雙行，第低壓閃存 |
| 文件頁數(shù)： | 18/37頁 |
| 文件大?。?/td> | 267K |
| 代理商： | M59DR008EN |
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M59DR008E, M59DR008F
18/37
POWER SUPPLY
Power Down
The memory provides Reset/Power Down control
input RP. The Power Down function can be acti-
vated only if the relevant Configuration Register bit
is set to ’1’. In this case, when the RP signal is
pulled at V
SS
the supply current drops to typically
I
CC2
(see Table 22), the memory is deselected and
the outputs are in high impedance.If RP is pulled
to V
SS
during a Program or Erase operation, this
operation is aborted in t
PLQ7V
and the memory
content is no longer valid (see Reset/Power Down
input description).
Power Up
The memory Command Interface is reset on Pow-
er Up to Read Array. Either E or W must be tied to
V
IH
during Power Up to allow maximum security
and the possibility to write a command on the first
rising edge of W.
Supply Rails
Normal precautions must be taken for supply volt-
age decoupling; each device in a system should
have the V
DD
rails decoupled with a 0.1μF capac-
itor close to the V
DD
, V
DDQ
and V
SS
pins. The PCB
trace widths should be sufficient to carry the re-
quired V
DD
program and erase currents.
Table 21. Program, Erase Times and Program, Erase Endurance Cycles
(T
A
= 0 to 70°C; V
DD
= V
DDQ
= 1.65V to 2.2V, V
PP
= V
DD
unless otherwise specified)
Note: 1. Max values refer to the maximum time allowed by the internal algorithm before error bit is set. Worst case conditions program or
erase should perform significantly better.
2. Excludes the time needed to execute the sequence for program instruction.
Parameter
M59DR008
Unit
Min
Max
(1)
Typ
Typical after
100k W/E Cycles
Parameter Block (4 KWord) Erase (Preprogrammed)
2.5
0.15
0.4
sec
Main Block (32 KWord) Erase (Preprogrammed)
10
1
3
sec
Bank Erase (Preprogrammed, Bank A)
2
6
sec
Bank Erase (Preprogrammed, Bank B)
2
6
sec
Chip Program
(2)
5
8
sec
Chip Program (DPG, V
PP
= 12V)
(2)
2.5
sec
Word Program
200
10
10
μs
Program/Erase Cycles (per Block)
100,000
cycles
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M59DR008F | 8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
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| M59DR008F100N6T | 8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M59DR008EZB | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
| M59DR008F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
| M59DR008F100N1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
| M59DR008F100N6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
| M59DR008F100ZB1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
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