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參數(shù)資料
| 型號(hào)： | M5913 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | Codec |
| 英文描述： | COMBINED SINGLE CHIP PCM CODEC AND FILTER |
| 中文描述： | 組合單芯片的PCM編解碼器和過(guò)濾器 |
| 文件頁(yè)數(shù)： | 15/17頁(yè) |
| 文件大?。?/td> | 220K |
| 代理商： | M5913 |
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OUTPUT GAIN SET: DESIGN CONSIDERA-
TIONS (refer to figure 4)
PWRO+ and PWRO– are low impedance comple-
mentary outputs. The voltages at the nodes are:
VO at PWRO+
VO at PWRO
VO =VO+VO– (total differential response)
R1 and R2 are a gain setting resistor network with
the center tap connected to the GSR input. A
value greater than 10K
and less than 100K for
R1 + R2 is recommended because:
a) The parallel combination of R1 + R2 and RL
sets the total loading.
b) The total capacitance at the GSR input and the
parallel combination of R1 and R2 define a
time constant which has to be minimized to
avoid inaccuracies.
If VA represents the output voltage without any
gain setting network connected, you can have:
VO =AVA
where A =
1
+(R1 /R2)
4
+(R1 /R2)
For design purposes, a useful form is R1/R2 as a
function of A.
R1 / R2 =
4A –
1
1 –A
(allowable values for A are those which make
R1/R2 positive)
Examples are:
If A = 1 (maximum output), then
R1/R2 =
∞ or V(GSR)= VO;
i.e., GSR is tied to PWRO+
If A = 1/2. then
R1/R2 = 2
If A = 1/4 (minimum output) then
R1/R2 = 0 or V(GSR)= VO+;
i.e., GSR is tied to PWRO+
DC CHARACTERISTICS (Tamb = 0 to 70
oC, VCC = +5V
± 5%, VBB =– 5V ± 5%, GRDA = 0V,unless oth-
erwise specified) Typical values are for Tamb =25
oC and nominal power supply values.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
DIGITAL INTERFACE
IIL
Low Level Input Current
GRDD
≤ VIN ≤ VIL (note 1)
10
A
IIH
High Level Input Current
VIH
≤ VIN ≤ VCC
10
A
VIL
Input Low Voltage, Except CLKSEL
0.8
V
VIH
Input High Voltage, Except CLKSEL
2.0
V
VOL
Output Low Voltage
IOL = 3.2mA at DX,TSX and
SIGR
0.4
V
VOH
Output High Voltage
IOH = 9.6mA at DX
IOH = 1.2mA at SIGR
2.4
V
VILO
Input Low Voltage, CLKSEL (note 2)
VBB
VBB +
0.5
V
VIIO
Input Intermediate Voltage, CLKSEL
GRDD
-0.5
0.5
V
VIHO
Input High Voltage, CLKSEL
VCC -
0.5
VCC
V
COX
Digital Output Capacitance (note 3)
5
pF
CIN
Digital Input Capacitance
5
10
pF
Notes:
1. VIN is the voltage on any digital pin.
2. SIGX and DCLKR are TTL level inputs between GRDD and VCC; they are also pinstraps for mode selection when tied to VBB.
Under these conditions VILO is the input low voltage requirement.
3. Timing parameters are guaranteed based on a 100pF load capacitance.
Up to eight digital outputs may be connected to a common PCM highway without buffering, assuming a board capacitance of 60pF.
M5913
7/17
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