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參數(shù)資料
| 型號(hào)： | M5913 |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | Codec |
| 英文描述： | COMBINED SINGLE CHIP PCM CODEC AND FILTER |
| 中文描述： | 組合單芯片的PCM編解碼器和過(guò)濾器 |
| 文件頁(yè)數(shù)： | 12/17頁(yè) |
| 文件大?。?/td> | 220K |
| 代理商： | M5913 |
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FUNCTIONAL DESCRIPTION
The M5913 provides the analog-to-digital and the
digital-to-analog conversion and the transmit and
receive filtering necessary to interface a full du-
plex (4 wires) voice telephone circuit with the
PCM highway of a time division multiplexed
(TDM) system. It is intended to be used at the
analog termination of a PCM line.
The following major functions are provided :
Bandpass filtering of the analog signals prior to
encoding and after decoding
Encoding and decoding of voice and call pro-
gress information
Encoding and decoding of the signaling and
supervision information
GENERAL OPERATION
System Reliability Features
The combo-chip can be powered up by pulsing
FSX and/or FSR while a TTL high voltage is ap-
plied to PDN, provided that all clocks and sup-
plies are connected. The M5913 has internal re-
sets on power up (or when VBB or VCC are
re-applied) in order to ensure validity of the digital
outputs and thereby maintain integrity of the PCM
highway.
On the transmit channel, digital outputs DX and
TS X are held in a high impedance state for ap-
proximately four frames (500
s) after power up or
application of VBB or VCC. After this delay, DX and
TSX will be functional and will occur in the proper
timeslot. The analog circuits on the transmit side
require approximately 40 milliseconds to reach
their equilibrium value due to the autozero circuit
setting time. Thus, valid digital information, such
as for on/off hook detection, is available almost
immediately, while analog information is available
after some delay.
On the receive channel, the digital output SIGR is
also held low for a maximum of four frames after
power up or application of VBB or VCC, SIGR will
remain low thereafter until it is updated by a sig-
naling frame.
To further enhance system reliability, TS X and DX
will be placed in a high impedance state approxi-
mately 20
s after an interruption of CLKX. Simi-
larly SIGR will be held low approximately 20
s af-
ter an interruption of CLKR. These interruptions
could possibly occur with some kind of fault con-
dition.
Power Down And Standby Modes
To minimize power consumption, two power down
modes are provided in which most M5913 func-
tions are disabled. Only the power down, clock,
and frame sync buffers, which are required to
power up the device, are enabled in these modes.
As shown in table 1, the digital outputs on the ap-
propriate channels are placed in a high imped-
ance state until the device returns to the active
mode.
The Power Down mode utilizes an external con-
trol signal to the PDN pin. In this mode, power
consumption is reduced to an average of 0.5mW.
The device is active when the signal is high and
inactive when it is low. In the absence of any sig-
nal, the PDN pin floats to TTL high allowing the
device to remain active continuously.
The Standby mode leaves the user an option of
powering either channel down separately or pow-
ering the entire down by selectively removing FSX
and/or FSR. With both channels in the standby
state, power consumption is reduced to an aver-
age of 1mW. If transmit only operation is desired,
FSX should be applied to the device while FSR is
held low. Similarly, if receive only operation is de-
sired, FSR should be applied while FSX is held
low.
Fixed Data Rate Mode
Fixed data rate timing, is selected by connecting
DCLKR to VBB. It employs master clock CLKX, and
CLKR, frame synchronization clocks FSX and
FSR, and output TS X.
CLKX, and CLKR, serve both as the master clock
to operate the codec and filter sections and bit
clocks to clock the data in and out from the PCM
highway. FSX and FSR are 8kHz inputs which set
the sampling frequency and distinguish between
signaling and non-signaling frames by thir pulse
width. A frame synchronization pulse which is one
master clock wide designates a non-signaling
frame, while a double wide sync pulse enables
Device Status
Power Down Methods
Digital Outputs Status
Power Down Mode
PDN = TTL low
TSX and DX are placed in a high impedance state and
SIGR is placed in a TTL low state within 10
s.
Stand-by Mode
FSX and FSR are TTL low
TSX and DX are placed in a high impedance state and
SIGR is placed in a TTL low state 30ms after FSX and
FSR are removed.
Only transmit is on stand-by
FSX is TTL low
TSX and DX are placed in a high impedance state
within 30ms.
Only receive is on stand-by
FSR is TTL low
SIGR is placed in a TTL low state within 30ms.
Table 1: Power Down Methods
M5913
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