參數(shù)資料
型號(hào)： M58LW064AT
廠商： 意法半導(dǎo)體
英文描述： 64 Mbit x16 and x16/x32, Block Erase Low Voltage Flash Memories
中文描述： 64兆位x16和x16/x32，塊擦除低壓閃存
文件頁(yè)數(shù)： 10/53頁(yè)
文件大小： 319K
代理商： M58LW064AT
M58LW064A, M58LW064B
10/53
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A1-A22).
A1 is used to select
between the high and low Word in the x16 config-
uration
of the M58LW064A
M58LW064B A1 is not used in the x32 mode.
When Chip Enable E is at V
IL
the address bus is
used to input addresses for the memory array in
Read mode, or addresses for the data to be pro-
grammed, or to input addresses associated with
Commands to be written to the Command Inter-
face. Theaddress latch is transparent when Latch
Enable L is at V
IL
. The address inputs for the
memory array are latched on the rising edge of
Chip Enable E or Latch Enable L or Write Enable
W, whichever occurs first in a writeoperation. The
address is also internally latched in the command
for an Erase or Program Instruction.
Data Inputs/Outputs (DQ0-DQ31).
Input
for a Write to Buffer and Program operationand for
writing Commands to the Command Interface are
latched on the rising edge of Write Enable W or
Chip Enable E, whichever occurs first.
When Chip Enable E and Output Enable G are at
V
IL
data is output from the Array, the Electronic
Signature - the Manufacturer and the Device code
- the Block Protection status, the CFI Query infor-
mation orthe Status Register.The databus is high
impedance when the device is deselected with
Chip Enable E at V
IH
, Output Enable Gis at V
IH
or
RP is at V
IL
. When the P/E.C. is active the Status
Register content is output on DQ0-DQ7and DQ8-
DQ31 are at V
IL
.
Chip Enable (E).
The Chip Enable E input acti-
vates the memory control logic, input buffers, de-
coders andsense amplifiers. Chip Enable E at V
IH
deselects thememory and reduces thepower con-
sumption to the standby level.
Output Enable (G).
The Output Enable G gates
the outputs through the data output buffers during
a read operation. When Output Enable G is at V
IH
the outputs are high impedance. Output Enable G
can be used to suspend the data output in a burst
read operation.
or B. For the
data
Write Enable (W).
The Write Enable W input
controls writing to the Command Interface, Input
Address and Data latches. Both addresses and
data are latched onthe rising edge of W (see also
Latch Enable L).
Reset/Power-down (RP).
The
down RP input provides a hardware reset of the
memory and power-down functions. Reset/Power-
down of the memory is achieved by pulling RP to
V
IL
for at least t
PLPH
. Writing is inhibited to protect
data, the Command Interface and the P/E.C. are
reset. The Status Register information is cleared
and power consumption is reducedto deep power-
down level. The device acts as deselected, that is
the data outputs are high impedance.
When RP rises to V
IH
, the device will be available
for new operations after a delay of t
PHQV
and will
be configured by default for Asynchronous Ran-
dom Read. The minimum delay required toaccess
the Command Interface by a write cycle is t
PHWL
.
If theRP input is activated during a Block Erase, a
Write toBuffer and Program ora Block Protect/Un-
protect operation the cycle is aborted and data is
altered and may be corrupted. The Ready/Busy
output RB may remain low for a maximum time of
t
PLPH
+ t
PHRH
beyond the completion of the Reset/
Power-down RP pulse.
Applying the higher voltage V
HH
tothe Reset/Pow-
er-down input RP temporarily unprotects and en-
ables Eraseand Program operations on allblocks.
Thus it acts as a hardware block unprotect input.
In an application, it is recommended to associate
RP to the reset signal of themicroprocessor. Oth-
erwise, if a reset operation occurswhile the device
is performing an Erase or Program cycle, the
Flash memory may output the Status Register in-
formation instead of being re-initialized to the de-
fault Asynchronous Random Read.
Latch Enable (L).
Latch EnableL latches the ad-
dress bits A1-A22 on its rising edge for the Asyn-
chronous Latch Enable Controlled Read or Write,
or Synchronous Burst Read operations. The ad-
dress latch is transparent when Latch Enable L is
at V
IL
. Latch Enable Lmust remain at V
IL
for Asyn-
chronous Random Read and Write operations.
Reset/Power-
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