參數(shù)資料
型號: M58LW064A150NF6T
廠商: 意法半導(dǎo)體
英文描述: 64 Mbit x16 and x16/x32, Block Erase Low Voltage Flash Memories
中文描述: 64兆位x16和x16/x32,塊擦除低壓閃存
文件頁數(shù): 22/53頁
文件大?。?/td> 319K
代理商: M58LW064A150NF6T
M58LW064A, M58LW064B
22/53
Block Unprotect Instruction (BU).
The
Unprotect Instruction BU uses a two-cycle write
sequence. All the Block Protect bits are simulta-
neously erased. The Block Protect bit register is
erased by giving the command 60h and then the
Confirm command D0h, at any address location.
The sequence is aborted if the Confirm command
is not given and the device will output the Status
Register Data with DQ4 and DQ5 set to ’1’.
Block Erase Instruction (EE).
The Block Erase
Instruction EE uses a two-cycle command se-
quence. The Erase Setup command 20h is written
to anyaddress location. Then a second writecycle
is given with the block address to be erased and
the Confirm command D0h. The sequence is
aborted if the Confirm command is not given and
the device willoutput the StatusRegister Datawith
DQ4 and DQ5 set to ’1’.
During the execution of the erase cycle by the P/
E.C., the memory accepts only the Erase/Program
Suspend instructions. Read operations output the
Status Register bits. A complete state of the erase
operation is given by the Status Register bits.
Erase/Program Suspend Instruction (PES).
The Block Erase or Write to Buffer and Program
operations may be suspended by writing the com-
mand B0h at any address. The Erase/Program
Suspend Instructioninterrupts theP/E.C. Eraseor
Program sequence at a predetermined point in the
algorithm. After the Suspend command is written
the device outputs the Status Register data.
It is possible to read or program data in a block
other thanthe one in whichthe Erase Suspend op-
eration is effective. It is only possible to read in a
block other than the one in which a Program Sus-
pend operation is effective. The suspended Erase/
Program operation has to be resumed in order to
complete the previous erase/program sequence.
The Erase Suspend instruction is accepted only
during a Block Erase operation execution. Pro-
gram Suspendalso is valid only during the Writeto
Buffer and Program instruction execution. Block
Erase or Erase/Program Suspend instructions are
Block
ignored if the memory is already in the Suspend
mode.
The Suspend Instructionmay be presented at any
time during the execution of a Block Erase. For a
Write to Buffer and Program instruction the Sus-
pend Instruction is accepted only when the P/E.C.
is running.
The device outputs information about thesuspend
in the Status Register information on DQ7, DQ6
and DQ2. If the operation has been completed
DQ7 = ’1’ and DQ6 = ’0’ (Erase Suspend) or
DQ2 = ’0’(Program Suspend).
If the Suspend instruction occurred after the P/
E.C. has completed its operation (DQ7 = 1,
DQ6 = 0 and DQ2 = 0), the Status Register infor-
mation remains available by toggling Output En-
able G. No command is accepted by the device
with the exception of a Read Memory Array In-
struction FFh. After the FFh Command is issued,
the device is ready for Read Array (in the mode
defined by the last Set Configuration Register is-
sued).
When a program operation is completed inside a
Block Erase Suspend Instruction, Read Array In-
struction FFh will reset the device to Read Array.
The Erase Resume Instruction has to be issued to
complete the whole sequence.
When erase is suspended, the memory will re-
spond only to the Read Array, Read Electronic
Signature, Read Query, Read Status Register,
Clear Status Register, Erase/Program Resume
and the Write to Buffer and Program instructions.
When a Write to Buffer and Program instruction is
suspended, the memory will respond only to the
Read Array, Read Electronic Signature, Read
Query, Read Status Register, Clear Status Regis-
ter and Erase/Program Resume instructions.
Erase/Program Resume Instruction(PER).
If
an Erase Suspend instruction was previously exe-
cuted, the erase operation may be resumed by
giving the command D0h, at any address. This
also serves as the Confirm command for the Write
to Buffer and Program (WPBR) Instruction which
is issued after the write buffer loading sequence is
completed, and which starts the P/E.C.
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