參數(shù)資料
型號: M58LW064A150NF6T
廠商: 意法半導(dǎo)體
英文描述: 64 Mbit x16 and x16/x32, Block Erase Low Voltage Flash Memories
中文描述: 64兆位x16和x16/x32,塊擦除低壓閃存
文件頁數(shù): 14/53頁
文件大小: 319K
代理商: M58LW064A150NF6T
M58LW064A, M58LW064B
14/53
M8 Valid Data Ready R Signal Configuration.
The Valid Data Ready R output signal indicates
when valid data is on the data outputs synchro-
nous with the valid burst clock egde. It can be as-
serted by the device synchronously with the valid
clock edge or one clock cycle before.
M7 Burst Type.
Accesses within a given burst may be pro-
grammed to be either Sequential or Interleaved.
This is referred to as the burst type and is selected
by theBurst Configuration RegisterM7bit. Theac-
cess order within a burst is determined by the
burst length, the burst type and the starting ad-
dress (See Table 8).
M6 Valid Clock Edge Configuration.
All the synchronous operations such as Burst
Read, Output Data or Ready signal validation can
be synchronized on the valid rising oron thefalling
edge of the Burst Clock signal K.
M2 - M0Burst Length.
Synchronous reads have a programmable burst
length, set using the M2- M0 bits of theBurst Con-
figuration Register. The burst length corresponds
to the maximum number of Words or Double-
Words that can be output. Burst lengths of 1, 2, 4
or 8 are available for both the Sequential and In-
terleaved burst types, and a continuous burst is
available for the Sequential type. The burst length
of 8 is not available in the x32 configuration.
When a Read command is issued, a block of
Words or Double-Words equal to the burst length
is selected. All accesses for that burst take place
within this block, meaning that the burst wraps
within the burst block if a boundary is reached.
If a Continuous Burst Read has been initiated the
device will output data synchronously. Depending
on the starting address of the read, the device ac-
tivates the Valid Data Ready R output to indicate
that it needs a delay to complete the internal read
operation before outputing data. If the starting ad-
dress is aligned to a four Word boundary the con-
tinuous burst mode will run without activating the
Valid Data Ready R output. If the starting address
is not aligned to a four Word boundary,Valid Data
Ready R is activated at the beginning of the con-
tinuous burst read to indicate that the device
needs an internal delay to read the content of the
four successive words in the array.
Pipelined Burst Read.
An overlapping Burst Read operation is possible.
That is, the address and data phases of consecu-
tive synchronous read operations can be over-
lapped by several clock cycles. This is done by
applying a pulse on Latch Enable Linput to latch a
new address before the completion of the data
output of the current cycle. This reduces or avoids
wait-states in the data output for the burst read
mode. The minimum clock edge number for the
following read sequence must be six before the
last data output of the previous read cycle. The
pipelined burst read mode is available in the x16
organisation for both burst length definitions of
four and eight, and in the x32 organisation for the
burst length of four. It is not possible for a burst
length of one or two.
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