參數(shù)資料
型號: M58LW032D90N1E
廠商: 意法半導(dǎo)體
英文描述: 32 Mbit 4Mb x8, 2Mb x16, Uniform Block 3V Supply Flash Memory
中文描述: 32兆位4Mb的× 8,功能的2Mb x16插槽,統(tǒng)一座3V電源快閃記憶體
文件頁數(shù): 11/51頁
文件大?。?/td> 748K
代理商: M58LW032D90N1E
11/51
M58LW032D
sistor. The use of an open-drain output allows the
STS pins from several memories to be connected
to a single pull-up resistor (a Low will indicate that
one, or more, of the memories is busy).
STS is not Low during a reset unless the reset was
applied when the Program/Erase controller was
active.
Program/Erase Enable (V
PEN
).
The
Erase Enable input, V
PEN,
is used to protect all
blocks, preventing Program and Erase operations
from affecting their data.
Program/Erase Enable must be kept High during
all Program/Erase Controller operations, other-
wise the operations is not guaranteed to succeed
and data may become corrupt.
V
DD
Supply Voltage.
V
DD
provides the power
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
Program/
V
DDQ
Supply Voltage.
V
DDQ
provides the power
supply to the I/O pins and enables all Outputs to
be powered independently from V
DD
. V
DDQ
can be
tied to V
DD
or can use a separate supply.
It is recommended to power-up and power-down
V
DD
and V
DDQ
together to avoid any condition that
would result in data corruption.
V
SS
Ground.
Ground, V
SS,
is the reference for
the core power supply. It must be connected to the
system ground.
V
SSQ
Ground.
V
SSQ
ground is the reference for
the input/output circuitry driven by V
DDQ
. V
SSQ
must be connected to V
SS
.
Note: Each device in a system should have
V
DD
and
V
DDQ
decoupled with a 0.1μF ceramic
capacitor close to the pin (high frequency, in-
herently low inductance capacitors should be
as close as possible to the package). See Fig-
ure 8, AC Measurement Load Circuit.
Table 2. Device Enable
Note: For single device operations, E2 and E1 can be connected to V
SS
.
E2
E1
E0
Device
V
IL
V
IL
V
IL
Enabled
V
IL
V
IL
V
IH
Disabled
V
IL
V
IH
V
IL
Disabled
V
IL
V
IH
V
IH
Disabled
V
IH
V
IL
V
IL
Enabled
V
IH
V
IL
V
IH
Enabled
V
IH
V
IH
V
IL
Enabled
V
IH
V
IH
V
IH
Disabled
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