參數(shù)資料
型號: M58LW032C90N6E
廠商: 意法半導(dǎo)體
英文描述: 32 Mbit 2Mb x16, Uniform Block, Burst 3V Supply Flash Memory
中文描述: 32兆位的2Mb x16插槽,統(tǒng)一座,突發(fā)3V電源快閃記憶體
文件頁數(shù): 17/61頁
文件大?。?/td> 845K
代理商: M58LW032C90N6E
17/61
M58LW032C
Table 3. Configuration Register
Note: 1. 4 - 2 - 2 - 2 (represents X-Y-Y-Y) is not allowed.
2. X latencies can be calculated as: (t
AVQV
– t
LLKH
+ t
QVKH
) + t
SYSTEM MARGIN
< (X -1) t
K.
(X
is an integer number from 4 to 8 and t
K
is the clock period).
3. Y latencies can be calculated as: t
KHQV
+ t
SYSTEM MARGIN
+ t
QVKH
< Y t
K.
4. t
SYSTEM MARGIN
is the time margin required for the calculation.
Address
Bit
Mnemonic
Bit Name
Reset
Value
Value
Description
16
CR15
Read Select
1
0
Synchronous Burst Read
1
Asynchronous Bus Read (default at power-up)
15
CR14
Reserved
14
to
12
CR13-CR11
X-Latency
(2)
XXX
001
Reserved
010
X-Latency = 4, 4-1-1-1 (use only with Y-Latency = 1)
(1)
011
X-Latency = 5, 5-1-1-1, 5-2-2-2
100
X-Latency = 6, 6-1-1-1, 6-2-2-2
101
X-Latency = 7, 7-1-1-1, 7-2-2-2
110
X-Latency = 8, 8-1-1-1, 8-2-2-2
11
CR10
Internal
Clock Divider
X
0
X and Y-Latencies remains as set in CR13-CR11 and
CR9
1
Divides internal clock, X and Y-Latencies multiplied by 2
10
CR9
Y-Latency
(3)
X
0
Y-Latency = 1
1
Y-Latency = 2
9
CR8
Valid Data
Ready
X
0
R valid Low during valid Clock edge
1
R valid Low one cycle before valid Clock edge
8
CR7
Burst Type
X
0
Interleaved
1
Sequential
7
CR6
Valid Clock
Edge
X
0
Falling Clock edge
1
Rising Clock edge
6 to 4
CR5-CR3
Reserved
3
to
1
CR2-CR0
Burst Length
XXX
001
4 Words
010
8 Words
111
Continuous
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M58LW032C90N6 32 Mbit 2Mb x16, Uniform Block, Burst 3V Supply Flash Memory
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