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參數(shù)資料
| 型號： | M54HC74 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR |
| 中文描述： | 雙D型觸發(fā)器與預(yù)置和清除 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 250K |
| 代理商： | M54HC74 |
M54HC74
M74HC74
October 1992
DUAL D TYPE FLIP FLOP WITH PRESET AND CLEAR
.
HIGH SPEED
f
MAX
= 71 MHz (TYP.) AT V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 2
μ
A(MAX.) AT T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
I
OH
= I
OL
= 4 mA (MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN ANDFUNCTION COMPATIBLE
WITH 54/74LS74
B1R
(Plastic Package)
ORDER CODES :
M54HC74F1R
M74HC74B1R
M74HC74M1R
M74HC74C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
INPUT AND OUTPUT EQUIVALENT CIRCUIT
The M54/74HC74 is a high speed CMOS DUAL D
TYPE FLOP WITH PRESET AND CLEAR fabri-
cated in silicon gate C
2
MOS technology. It has the
same high speed performance of LSTTL combined
withtrueCMOSlowpower consumption. Asignal on
the DINPUT istransferred to the QOUTPUTduring
the positive going transition of the clock pulse.
CLEARand PRESET are independent of the clock
and accomplished by alowontheappropriate input.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
DESCRIPTION
1/11
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PDF描述 |
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| M54HC75 | 4 BIT D TYPE LATCH |
| M54HC75D | RAD HARD 4 BIT D TYPE LATCH |
| M54HC75D1 | RAD HARD 4 BIT D TYPE LATCH |
| M54HC75K | RAD HARD 4 BIT D TYPE LATCH |
| M54HC75K1 | RAD HARD 4 BIT D TYPE LATCH |
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| M54HC86K | 制造商:STMicroelectronics 功能描述: |
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| M54HCT244K1 | 制造商:STMicroelectronics 功能描述: |
| M54HCT245K | 制造商:STMicroelectronics 功能描述:LOGIC, 5VOLTSOCTAL BUSOCTAL BUS TRANSCEIVER - 3-STATEFLAT-20 - Bulk |
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