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參數(shù)資料
| 型號： | M54HC73F1R |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | High-Output-Drive Operational Amplifier 8-MSOP-PowerPAD -40 to 125 |
| 中文描述： | 雙JK觸發(fā)器亂竄預(yù)置和清除 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 247K |
| 代理商： | M54HC73F1R |
M54HC73
M74HC73
October 1992
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
LOWPOWER DISSIPATION
I
CC
= 2
μ
A(MAX.) AT T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
IOH
= I
OL
= 4 mA(MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN AND FUNCTION COMPATIBLE WITH
54/74LS73
B1R
(Plastic Package)
ORDER CODES :
M54HC73F1R
M74HC73B1R
M74HC73M1R
M74HC73C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
INPUT AND OUTPUT EQUIVALENT CIRCUIT
.
HIGH SPEED
f
MAX
= 75 MHz (TYP.) AT V
CC
= 5 V
The M54/74HC73 is a high speedCMOSDUAL J-K
FLIP FLOP WITH CLEAR fabricated in silicon gate
C
2
MOStechnology.Ithas thesame highspeedper-
formance of LSTTL combined with true CMOS low
power consumption. Depending on the logic level
applied to J and K inputs, this device changes state
on the negative going transition of clock input pulse
(CK). The clear function is accomplished inde-
pendentlyof theclock conditionwhen theclearinput
(CLR)is taken low.All inputs are equipped withpro-
tectioncircuitsagainst staticdischarge and transient
excess voltage.
DESCRIPTION
1/11
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