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參數(shù)資料
| 型號(hào)： | M54HC40102B1R |
| 廠商： | 意法半導(dǎo)體 |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS |
| 中文描述： | 8階段預(yù)置同步向下計(jì)數(shù)器 |
| 文件頁(yè)數(shù)： | 2/14頁(yè) |
| 文件大小： | 300K |
| 代理商： | M54HC40102B1R |
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When the ASYNCHRONOUS PRESET-ENABLE
(APE)input islow,data attheJ inputs isasynchron-
ouslyforced into thecounter regardless of the state
of the SPE, CI/CE, orCLOCK inputs. J InputsJ0-J7
representtwo4-bit BCDwordsforthe HC40102 and
a single 8-bit binary word for the HC40103. When
the CLEAR (CLR input is low, the counter is asyn-
chronously cleared to its maximum count (99
10
for
the HC40102 and 255
10
for the HC40103 regard-
less of the state of any other input. The precedence
relationship between control inputis indicated in the
truthtable. If all control inputs are high at the time of
zero count, the counters will jump to the maximum
count, giving a counting sequence of 100 pr 256
clockpulses long. The HC40102andHC40103 may
be cascaded using the CI/CEinput and the CO/ZD
output, in either a synchronous or ripple mode. All
inputs are equipped with protection circuits against
static discharge and transient excess voltage.
DESCRIPTION
(Continued)
TRUTH TABLE
CONTROL INPUTS
CLEAR
APE
H
H
MODE
FUNCTIONAL DESCRIPTION
SPE
H
CI/CE
H
COUNT INHIBIT
EVEN IF CLOCK IS GIVEN, NO COUNT IS
MADE
DOWN COUNT AT RISING EDGE OF CLOCK
DATA OF PI TERMINAL IS PRESET AT
RISING EDGE OF CLOCK
DATA PF PI TERMINAL IS
ASYNCHRONOUSLY PRESET TO CLOCK
COUNTER IS SET TO MAXIMUM COUNT
H
H
H
H
H
L
L
X
REGULAR COUNT
SYNCHRONOUS PRESET
H
L
X
X
ASYNCRONOUS PRESET
L
X
X
X
CLEAR
X: DON’T CARE -MAXIMUM COUNT:”99” FORHC40102AND ”255”:FORHC40103
LOGIC DIAGRAM
(HC40102)
M54/M74HC40102/40103
2/14
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| M54HC40102C1R | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS |
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