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參數(shù)資料
| 型號(hào)： | M54HC242F1R |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | QUAD BUS TRANSCEIVER 3-STATE |
| 中文描述： | 四總線收發(fā)器三態(tài) |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 257K |
| 代理商： | M54HC242F1R |
M54/74HC242
M54/74HC243
October 1993
QUAD BUS TRANSCEIVER (3-STATE)
B1R
(Plastic Package)
ORDER CODES :
M54HCXXXF1R
M74HCXXXB1R
M74HCXXXM1R
M74HCXXXC1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
INPUT AND OUTPUT EQUIVALENT CIRCUIT
DESCRIPTION
The M54/74HC242/243 are high speed CMOS
QUAD
BUS
TRANSCEIVER
FABRICATED
IN
SILICON
technology. They have the same high speed
performance of LSTTL combined with true CMOS
low power consumption. The HC242/243 are 3
STATE bi-directional inverting and non-inverting
buffersandare intended for two-way asynchronous
communication between data buses. They are high
drive current outputs which enable high speed
operation when driving large bus capacitances.
Each device hasone active high enable (GBA), and
one active low enable (GAB). GBA enables the A
outputs and GAB enables the B outputs. All inputs
are equipped with protection circuits against static
discharge and transient excess voltage.
.
HIGH SPEED
t
PD
= 9 ns (TYP.) AT V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT 25
°
C
.
OUTPUT DRIVE CAPABILITY
15 LSTTL LOADS
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
SYMMETRICAL OUTPUT IMPEDANCE
I
OL
=
I
OH
= 6 mA(MIN.)
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN ANDFUNCTION COMPATIBLE
WITH 54/74LS242/243
(3-STATE)
C
2
MOS
GATE
HC243
HC242
1/11
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