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參數(shù)資料
| 型號(hào)： | M54HC259F1R |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8 BIT ADDRESSABLE LATCH |
| 中文描述： | 8位可尋址鎖存 |
| 文件頁(yè)數(shù)： | 1/12頁(yè) |
| 文件大小： | 264K |
| 代理商： | M54HC259F1R |
M54HC259
M74HC259
October 1992
8 BIT ADDRESSABLE LATCH
B1R
(Plastic Package)
ORDER CODES :
M54HC259F1R
M74HC259B1R
M74HC259M1R
M74HC259C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
.
HIGH SPEED
t
PD
= 15 ns(TYP.) at V
CC
= 5 V
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) at T
A
= 25
°
C
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL PROPAGATION DELAYS
IOH
= I
OL
= 4 mA(MIN.)
.
BALANCEDPRORAGATION DELAYS
t
PLH
= t
PHL
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V to 6 V
.
PIN AND FUNCTION COMPATIBLE WITH
54/74LS259
DESCRIPTION
The M54/74HC259 is a high speed CMOS 8 BIT
ADDRESSABLE LATCH fabricated in silicon gate
C
2
MOStechnology.Ithas thesame highspeedper-
formance of LSTTL combined with true CMOS low
powerconsumption.
The M54HC259/M74HC259 has single data input
(D) 8 latch outputs (Q0-Q7), 3 address inputs (A,B,
and C), common enable input (E), and a common
CLEARinput.To operate this device asanaddress-
able latch, data is held on the D input, and the ad-
dressof thelatchintowhich thedataistobeentered
is held on the A, B, and C inputs. WhenENABLE is
taken low the data flows through to the addresses
output. The data is stored on the positive-going
edgeofthe ENABLE pulse. Allunaddressed latches
will remain unaffected. With ENABLE in the high
statethedeviceisdeselected and all latches remain
intheirprevious state,unaffected bychanges onthe
data or address inputs. To eliminate the possibility
of entering erroneous data into the latches, the EN-
ABLE should be held high (inactive) while the ad-
dresslinesarechanging. IfENABLE isheldhighand
CLEARis takenlow all eight latches are cleared to
the lowstate.IfENABLE islowall latchesexceptthe
addressed latch will be cleared. The addressed
latchwillinsteadfollowthe Dinput, effectivelyimple-
menting a 3-to8 line decoder.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
1/12
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