參數(shù)資料
型號(hào): M52S32162A-7.5BG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類(lèi): DRAM
英文描述: 1M x 16Bit x 2Banks Synchronous DRAM
中文描述: 2M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54
封裝: 8 X 8 MM, LEAD FREE, VFBGA-54
文件頁(yè)數(shù): 17/30頁(yè)
文件大?。?/td> 787K
代理商: M52S32162A-7.5BG
ES MT
Page Read Cycle at Different Bank @ Burst Length=4
M52S32162A
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Apr. 2007
Revision
:
1.2
17/30
*Note: 1.CS can be don’t cared when RAS , CAS and
WE
are high at the clock high going dege.
2.To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.
CLOCK
CKE
CS
RAS
CAS
BA
ADDR
A10/AP
CL=2
CL=3
WE
DQM
HIGH
*Note2
RAa
CAa
RBb
RAa
Read
(A-Bank)
Row Active
Row Active
(B-Bank)
(A-Bank)
Read
(A-Bank)
Read
(B-Bank)
Read
(A-Bank)
Read
(B-Bank)
Precharge
(A-Bank)
: Don't care
DQ
CBb
CAc
CBd
CAe
QAa0
*Note1
RBb
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
QAa1 QAa2 QAa3
QBb0
QBb1 QBb2
QBb3
QAc0
QAc1 QBd0
QBd1
QAe0
QAe1
QAa0 QAa1 QAa2 QAa3
QBb0 QBb1
QBb2 QBb3
QAc0
QAc1 QBd0
QBd1 QAe0
QAe1
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