參數(shù)資料
型號: M52D32162A-10TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 1M x 16Bit x 2Banks Synchronous DRAM
中文描述: 2M X 16 SYNCHRONOUS DRAM, 8 ns, PDSO54
封裝: 0.400 INCH, LEAD FREE, TSOP2-54
文件頁數(shù): 7/30頁
文件大?。?/td> 784K
代理商: M52D32162A-10TG
ES MT
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
M52D32162A
Elite Semiconductor Memory Technology Inc.
Publication Date
:
May. 2007
Revision
:
1.4
7/30
-7.5
-10
Parameter
Symbol
Min
7.5
12
-
-
Max
Min
9
15
-
-
Max
Unit
Note
CAS Latency =3
CAS Latency =2
CAS Latency =3
CAS Latency =2
CLK cycle time
t
CC
1000
1000
ns
1
7
10
8
10
CLK to valid
output delay
t
SAC
ns
1
Output data hold time
t
OH
2.0
-
2.0
-
ns
2
CLK high pulse width
t
CH
2.5
-
2.5
-
ns
3
CLK low pulse width
t
CL
2.5
-
2.5
-
ns
3
Input setup time
t
SS
2.5
-
2.5
-
ns
3
Input hold time
t
SH
1.5
-
1.5
-
ns
3
CLK to output in Low-Z
t
SLZ
1
-
-
6
1
-
-
7
ns
2
CAS Latency =3
CLK to output in
Hi-Z
CAS Latency =2
t
SHZ
-
9
-
10
ns
-
*All AC parameters are measured from half to half.
Note:
1.Parameters depend on programmed CAS latency.
2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.
3.Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the
parameter.
相關PDF資料
PDF描述
M52D32162A-7.5BG 1M x 16Bit x 2Banks Synchronous DRAM
M52D32162A-7.5TG 1M x 16Bit x 2Banks Synchronous DRAM
M52D32321A 512K x 32Bit x 2Banks Synchronous DRAM
M52D32321A-10BG 512K x 32Bit x 2Banks Synchronous DRAM
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參數(shù)描述
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