參數(shù)資料
型號: M50LPW040N5T
廠商: 意法半導(dǎo)體
英文描述: 4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory
中文描述: 4兆位512KB的× 8,統(tǒng)一座3V電源低引腳數(shù)快閃記憶體
文件頁數(shù): 3/36頁
文件大小: 272K
代理商: M50LPW040N5T
3/36
M50LPW040
Table 1. Signal Names (LPC Interface) Memory
Note: 1. Pin 9 in the PLCC32, and Pin 21 in the TSOP40, may also
be driven High or driven Low.
LAD0-LAD3
Input/Output Communications
LFRAME
Input Communication Frame
ID0-ID2
Identification Inputs
GPI0-GPI4
General Purpose Inputs
IC
Interface Configuration
RP
Interface Reset
INIT
CPU Reset
CLK
Clock
TBL
Top Block Lock
WP
Write Protect
RFU
1
Reserved for Future Use. Leave
disconnected
V
CC
Supply Voltage
V
PP
Optional Supply Voltage for Fast
Erase Operations
V
SS
Ground
NC
Not Connected Internally
Figure 4. PLCC Connections
Note: Pins 27 and 28 are not internally connected.
AI05438
G
NC
VSS
VCC
INIT
LFRAME
RFU
R
17
ID1
ID0
LAD0
L
L
L
R
GPI1
GPI0
WP
TBL
RFU
ID2
9
C
1
R
NC
G
RFU
32
V
V
M50LPW040
G
IC (VIL)
R
25
V
A1
A0
DQ0
A7
A6
A5
A4
A3
A2
A
R
R
A
V
V
A
NC
VSS
VCC
G
W
RB
NC
DQ7
IC (VIH)
D
D
D
D
D
D
V
A/A Mux
A/A Mux
A/A Mux
A/A Mux
current PC Chipsets; the M50LPW040 acts as the
PC BIOS on the Low Pin Count bus for these PC
Chipsets.
The secondary interface, the Address/Address
Multiplexed (or A/A Mux) Interface, is designed to
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
The memory is offered in TSOP40 (10 x 20mm)
and PLCC32 packages and it is supplied with all
the bits erased (set to ’1’).
SIGNAL DESCRIPTIONS
There are two different bus interfaces available on
this part. The active interface is selected before
power-up or during Reset using the Interface Con-
figuration Pin, IC.
The signals for each interface are discussed in the
Low Pin Count (LPC) Signal Descriptions section
and the Address/Address Multiplexed (A/A Mux)
Signal Descriptions section below. The supply sig-
nals are discussed in the Supply Signal Descrip-
tions section below.
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