參數(shù)資料
型號: M50LPW012K1T
廠商: 意法半導體
英文描述: 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory
中文描述: 2兆位的256Kb × 8,啟動塊3V電源低引腳數(shù)快閃記憶體
文件頁數(shù): 3/35頁
文件大?。?/td> 239K
代理商: M50LPW012K1T
3/35
M50LPW012
Table 1. Signal Names (LPC Interface) Memory
LAD0-LAD3
Input/Output Communications
LFRAME
Input Communication Frame
ID0-ID3
Identification Inputs
GPI0-GPI4
General Purpose Inputs
IC
Interface Configuration
RP
Interface Reset
INIT
CPU Reset
CLK
Clock
TBL
Top Block Lock
WP
Write Protect
RFU
Reserved for Future Use. Leave
disconnected or set at V
IL
or V
IH
.
V
CC
Supply Voltage
V
PP
Optional Supply Voltage for Fast
Erase Operations
V
SS
Ground
NC
Not Connected Internally
current PC Chipsets; the M50LPW012 acts as the
PC BIOS on the Low Pin Count bus for these PC
Chipsets.
The secondary interface, the Address/Address
Multiplexed (or A/A Mux) Interface, is designed to
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
The memory is offered in a PLCC32 package and
is supplied with all the bits erased (set to 1).
System Memory Mapping
The LPC address sequence is 32 bits long. The
M50LPW012 responds to addresses mapped to
the top of the 4 GByte memory space, from
FFFF FFFFh. Address bits A31-A24, A22 must be
set to 1. A23 is set to 1 for array access, and to 0
for register access.
The M50LPW012 also responds to addresses
mapped to the bottom of the 4 GByte memory
space, from 0000 0000h. Address bits A31-A24,
A22 must be set to 0. A23 is set to 0 for array
access, and to 1 for register access.
For A21-A18, see Table 2. A17-A0 are for array
addresses.
Table 2. Memory Identification Input Configuration
Memory
Number
ID2
ID2
ID1
ID0
Top
Bottom
A
21
A
20
A
19
A
18
A
21
A
20
A
19
A
18
1 (Boot)
V
IL
or floating V
IL
or floating V
IL
or floating V
IL
or floating
1
1
1
1
0
0
1
1
2
V
IL
or floating V
IL
or floating V
IL
or floating
V
IH
1
1
1
0
0
0
1
0
3
V
IL
or floating V
IL
or floating
V
IH
V
IL
or floating
1
1
0
1
0
0
0
1
4
V
IL
or floating V
IL
or floating
V
IH
V
IH
1
1
0
0
0
0
0
0
5
V
IL
or floating
V
IH
V
IL
or floating V
IL
or floating
1
0
1
1
0
1
1
1
6
V
IL
or floating
V
IH
V
IL
or floating
V
IH
1
0
1
0
0
1
1
0
7
V
IL
or floating
V
IH
V
IH
V
IL
or floating
1
0
0
1
0
1
0
1
8
V
IL
or floating
V
IH
V
IH
V
IH
1
0
0
0
0
1
0
0
9
V
IH
V
IL
or floating V
IL
or floating V
IL
or floating
0
1
1
1
1
0
1
1
10
V
IH
V
IL
or floating V
IL
or floating
V
IH
0
1
1
0
1
0
1
0
11
V
IH
V
IL
or floating
V
IH
V
IL
or floating
0
1
0
1
1
0
0
1
12
V
IH
V
IL
or floating
V
IH
V
IH
0
1
0
0
1
0
0
0
13
V
IH
V
IH
V
IL
or floating V
IL
or floating
0
0
1
1
1
1
1
1
14
V
IH
V
IH
V
IL
or floating
V
IH
0
0
1
0
1
1
1
0
15
V
IH
V
IH
V
IH
V
IL
or floating
0
0
0
1
1
1
0
1
16
V
IH
V
IH
V
IH
V
IH
0
0
0
0
1
1
0
0
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