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參數(shù)資料
| 型號(hào)： | M50LPW002K1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| 中文描述： | 2兆位的256Kb × 8，啟動(dòng)塊3V電源低引腳數(shù)快閃記憶體 |
| 文件頁數(shù)： | 12/39頁 |
| 文件大?。?/td> | 258K |
| 代理商： | M50LPW002K1T |
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M50LPW002
12/39
Address/Address Multiplexed (A/A Mux) Bus
Operations
The Address/Address Multiplexed (A/A Mux)
Interface has a more traditional style interface.
The signals consist of a multiplexed address
signals (A0-A10), data signals, (DQ0-DQ7) and
three control signals (RC, G, W). An additional
signal, RP, can be used to reset the memory.
The Address/Address Multiplexed (A/A Mux)
Interface
is
included
Programming equipment
programming. Only a subset of the features
available to the Low Pin Count (LPC) Interface are
available; these include all the Commands but
exclude the Security features and other registers.
The following operations can be performed using
the appropriate bus cycles: Bus Read, Bus Write,
Output Disable and Reset.
When the Address/Address Multiplexed (A/A Mux)
Interface is
selected all the blocks
unprotected. It is not possible to protect any blocks
through this interface.
Bus Read.
Bus Read operations are used to
output the contents of the Memory Array, the
Electronic Signature and the Status Register. A
valid Bus Read operation begins by latching the
Row Address and Column Address signals into
the memory using the Address Inputs, A0-A10,
and the Row/Column Address Select RC. Then
Write Enable (W) and Interface Reset (RP) must
be High, V
IH
, and Output Enable, G, Low, V
IL
, in
for
use
faster factory
by
Flash
for
are
order to perform a Bus Read operation. The Data
Inputs/Outputs will output the value, see Figure
12, Read AC Waveforms (A/A Mux Interface), and
Table 25, Read AC Characteristics (A/A Mux
Interface), for details of when the output becomes
valid.
Bus Write.
Bus Write operations write to the
Command Interface. A valid Bus Write operation
begins by latching the Row Address and Column
Address signals into the memory using the
Address Inputs, A0-A10, and the Row/Column
Address Select RC. The data should be set up on
the Data Inputs/Outputs; Output Enable, G, and
Interface Reset, RP, must be High, V
IH
and Write
Enable, W, must be Low, V
IL
. The Data Inputs/
Outputs are latched on the rising edge of Write
Enable, W. See Figure 13, Write AC Waveforms
(A/A Mux Interface), and Table 26, Write AC
Characteristics (A/A Mux Interface), for details of
the timing requirements.
Output Disable.
The data outputs are high-im-
pedance when the Output Enable, G, is at V
IH
.
Reset.
During Reset mode all internal circuits are
switched off, the memory is deselected and the
outputs are put in high-impedance. The memory is
in Reset mode when RP is Low, V
IL
. RP must be
held Low, V
IL
for t
PLPH
. If RP is goes Low, V
IL
,
during a Program or Erase operation, the
operation is aborted and the memory cells affected
no longer contain valid data; the memory can take
up to t
PLRH
to abort a Program or Erase operation.
Table 7. A/A Mux Bus Operations
Table 8. Manufacturer and Device Codes
Operation
G
W
RP
V
PP
DQ7-DQ0
Bus Read
V
IL
V
IH
V
IH
Don’t Care
Data Output
Bus Write
V
IH
V
IL
V
IH
V
CC
or V
PPH
Data Input
Output Disable
V
IH
V
IH
V
IH
Don’t Care
Hi-Z
Reset
V
IL
or V
IH
V
IL
or V
IH
V
IL
Don’t Care
Hi-Z
Operation
G
W
RP
A17-A1
A0
DQ7-DQ0
Manufacturer Code
V
IL
V
IH
V
IH
V
IL
V
IL
20h
Device Code
V
IL
V
IH
V
IH
V
IL
V
IH
31h
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| M50LPW002K5T | 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW012 | 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW012K | 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW012K1T | 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M50LPW002K5T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW012 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW012K | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW012K1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW040 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
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