參數(shù)資料
型號: M50LPW002K1T
廠商: 意法半導體
英文描述: 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory
中文描述: 2兆位的256Kb × 8,啟動塊3V電源低引腳數(shù)快閃記憶體
文件頁數(shù): 11/39頁
文件大?。?/td> 258K
代理商: M50LPW002K1T
11/39
M50LPW002
Table 6. Bus Write Field Definitions (LPC Interface)
Figure 6. Bus Write Waveforms (LPC Interface)
Clock
Cycle
Number
Clock
Cycle
Count
Field
LAD0-
LAD3
Memory
I/O
Description
1
1
START
0000b
I
On the rising edge of CLK with LFRAME Low, the contents
of LAD0-LAD3 must be 0000b to indicate the start of a LPC
cycle.
2
1
CYCTY
PE +
DIR
011Xb
I
Indicates the type of cycle. Bits 3:2 must be 01b. Bit 1
indicates the direction of transfer: 1b for write. Bit 0 is don’t
care (X).
3-10
8
ADDR
XXXX
I
A 32-bit address phase is transferred starting with the most
significant nibble first. A23-A31 must be set to 1. A22 = 1 for
Array, A22 = 0 for registers access. For A18-A21 values,
refer to Table 3.
11-12
2
DATA
XXXX
I
Data transfer is two cycles, starting with the least significant
nibble.
13
1
TAR
1111b
I
The host drives LAD0-LAD3 to 1111b to indicate a
turnaround cycle.
14
1
TAR
1111b
(float)
O
The LPC Flash Memory takes control of LAD0-LAD3 during
this cycle.
15
1
SYNC
0000b
O
The LPC Flash Memory drives LAD0-LAD3 to 0000b,
indicating it has received data or a command.
16
1
TAR
1111b
O
The LPC Flash Memory drives LAD0-LAD3 to 1111b,
indicating a turnaround cycle.
17
1
TAR
1111b
(float)
N/A
The LPC Flash Memory floats its outputs and the host takes
control of LAD0-LAD3.
AI04430
CLK
LFRAME
LAD0-LAD3
Number of
clock cycles
START
CYCTYPE
+ DIR
ADDR
DATA
TAR
SYNC
TAR
1
1
8
2
2
1
2
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