參數(shù)資料
型號： M50FW080N5TP
廠商： 意法半導體
英文描述： 8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
中文描述： 8兆1兆× 8，統(tǒng)一座3V電源閃存固件集線器
文件頁數(shù)： 17/56頁
文件大小： 292K
代理商： M50FW080N5TP
M50FW080
Bus operations
17/55
3
Bus operations
The two interfaces have similar bus operations but the signals and timings are completely
different. The Firmware Hub (FWH) Interface is the usual interface and all of the functionality
of the part is available through this interface. Only a subset of functions are available
through the Address/Address Multiplexed (A/A Mux) Interface.
See the sections: The
Firmware Hub (FWH) bus operations
and
Address/Address
Multiplexed (A/A Mux) bus operations
, for details of the bus operations on each interface.
3.1
Firmware Hub (FWH) bus operations
The Firmware Hub (FWH) Interface consists of four data signals (FWH0-FWH3), one control
line (FWH4) and a clock (CLK). In addition protection against accidental or malicious data
corruption can be achieved using two further signals (TBL and WP). Finally two reset
signals (RP and INIT) are available to put the memory into a known state.
The data signals, control signal and clock are designed to be compatible with PCI electrical
specifications. The interface operates with clock speeds up to 33MHz.
The following operations can be performed using the appropriate bus cycles: Bus Read, Bus
Write, Standby, Reset and Block Protection.
3.1.1
Bus Read
Bus Read operations read from the memory cells, specific registers in the Command
Interface or Firmware Hub Registers. A valid Bus Read operation starts when Input
Communication Frame, FWH4, is Low, V
IL
, as Clock rises and the correct Start cycle is on
FWH0-FWH3. On the following clock cycles the Host will send the Memory ID Select,
Address and other control bits on FWH0-FWH3. The memory responds by outputting Sync
data until the wait-states have elapsed followed by Data0-Data3 and Data4-Data7.
See
Table 4
and
Figure 6
, for a description of the Field definitions for each clock cycle of the
transfer. See
Table 22
and
Figure 11
, for details on the timings of the signals.
3.1.2
Bus Write
Bus Write operations write to the Command Interface or Firmware Hub Registers. A valid
Bus Write operation starts when Input Communication Frame, FWH4, is Low, V
IL
, as Clock
rises and the correct Start cycle is on FWH0-FWH3. On the following Clock cycles the Host
will send the Memory ID Select, Address, other control bits, Data0-Data3 and Data4-Data7
on FWH0-FWH3. The memory outputs Sync data until the wait-states have elapsed.
See
Table 5
and
Figure 7
, for a description of the Field definitions for each clock cycle of the
transfer. See
Table 22
and
Figure 11
, for details on the timings of the signals.
相關(guān)PDF資料
PDF描述
M50FW080NB5P 8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
M50FW080NB5TP 8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
M50LPW002 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory
M50LPW002K 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory
M50LPW002K1T 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M50FW080NB1 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
M50FW080NB1G 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
M50FW080NB1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
M50FW080NB1TG 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
M50FW080NB5 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 1Mb x8, Uniform Block 3V Supply Firmware Hub Flash Memory
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*